According to spec, we should check if output_bpp * pixel_rate is less
than DDI clock * 72, if UHBR is used.
HSDES: 1406899791
BSPEC: 49259
v2: - Removed wrong comment(Rodrigo Vivi)
- Added HSDES to the commit msg(Rodrigo Vivi)
- Moved UHBR check to the MST specific code
v3: - Changed commit subject(Rodrigo Vivi)
- Fixed the error message if check fails(Rodrigo Vivi)
v4: - Move UHBR check to new helper function
- Now both for non-DSC/DSC we use that new check as
one of the constraints, when figuring out output bpp
to be used(Ville Syrjälä)
v5: - Use symbol clock (32 bit per lane for DP2) instead of port
clock in the formula(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovs...@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index e3e7c305fece..e63132557690 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -47,8 +47,21 @@
static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int
bpp,
const struct drm_display_mode
*adjusted_mode,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc_state *pipe_config)
{
+ if (intel_dp_is_uhbr(pipe_config)) {
+ int output_bpp = bpp;
+ /* DisplayPort 2 128b/132b, bits per lane is always 32 */
+ int symbol_clock = pipe_config->port_clock / 32;
+
+ if (output_bpp * adjusted_mode->crtc_clock >=
+ symbol_clock * 72) {
+ drm_dbg_kms(&i915->drm, "UHBR check failed(required bw
%d available %d)\n",
+ output_bpp * adjusted_mode->crtc_clock,
symbol_clock * 72);
+ return -EINVAL;
+ }
+ }
+
return 0;
}
--
2.37.3
