Disabling ILK+ watermarks on failure to read the watermark levels dates
back to 2010 and commit 7f8a85698f5c ("drm/i915: Add the support of
memory self-refresh on Ironlake"), with no explanations, and it's been
copied and modified from that ever since. Finally drop it.If the value are actually zero, the ilk_compute_*_wm() functions should handle it gracefully. Cc: Ville Syrjälä <[email protected]> Suggested-by: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> --- drivers/gpu/drm/i915/display/i9xx_wm.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c index 50cdfe11192e..3d4687efe4dd 100644 --- a/drivers/gpu/drm/i915/display/i9xx_wm.c +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c @@ -4007,19 +4007,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv) /* For FIFO watermark updates */ if (HAS_PCH_SPLIT(dev_priv)) { ilk_setup_wm_latency(dev_priv); - - if ((DISPLAY_VER(dev_priv) == 5 && dev_priv->display.wm.pri_latency[1] && - dev_priv->display.wm.spr_latency[1] && dev_priv->display.wm.cur_latency[1]) || - (DISPLAY_VER(dev_priv) != 5 && dev_priv->display.wm.pri_latency[0] && - dev_priv->display.wm.spr_latency[0] && dev_priv->display.wm.cur_latency[0])) { - dev_priv->display.funcs.wm = &ilk_wm_funcs; - } else { - ilk_init_lp_watermarks(dev_priv); - drm_dbg_kms(&dev_priv->drm, - "Failed to read display plane latency. " - "Disable CxSR\n"); - dev_priv->display.funcs.wm = &nop_funcs; - } + dev_priv->display.funcs.wm = &ilk_wm_funcs; } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { vlv_setup_wm_latency(dev_priv); dev_priv->display.funcs.wm = &vlv_wm_funcs; -- 2.34.1
