> -----Original Message-----
> From: Intel-gfx <[email protected]> On Behalf Of Suraj
> Kandpal
> Sent: Tuesday, February 7, 2023 1:14 PM
> To: [email protected]
> Subject: [Intel-gfx] [PATCH v9 6/7] drm/i915/vdsc: Check slice design
> requirement
>
> Add function to check if slice design requirements are being met as defined
> in Bspec:
> 49259 in the section Slice Design Requirement
>
> --v7
> -remove full bspec link [Jani]
> -rename intel_dsc_check_slice_design_req to intel_dsc_slice_dimensions_valid
> [Jani]
>
> --v8
> -fix condition to check if slice width and height are of two -fix minimum
> pixel in slice
> condition
>
> Signed-off-by: Suraj Kandpal <[email protected]>
> ---
> drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 13ad853e24eb..6ebefc195e83 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -447,6 +447,29 @@ calculate_rc_params(struct rc_parameters *rc,
> }
> }
>
> +static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state
> *pipe_config,
> + struct drm_dsc_config *vdsc_cfg) {
> + if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB ||
> + pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
> + if (vdsc_cfg->slice_height > 4095)
> + return -EINVAL;
> + if (vdsc_cfg->slice_height * vdsc_cfg->slice_width >= 15000)
This should be greater than 15000 for valid case, please check
> + return -EINVAL;
> + } else if (pipe_config->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420) {
> + if (vdsc_cfg->slice_width % 2)
> + return -EINVAL;
> + if (vdsc_cfg->slice_height % 2)
> + return -EINVAL;
> + if (vdsc_cfg->slice_height > 4094)
> + return -EINVAL;
> + if (vdsc_cfg->slice_height * vdsc_cfg->slice_width >= 30000)
This should be greater than 30000 for valid case, please check
> + return -EINVAL;
> + }
> +
> + return 0;
If code reaches here, format is 422 which should be EINVAL as of now.
> +}
> +
> int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) {
> struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> @@ -455,11 +478,20 @@ int intel_dsc_compute_params(struct intel_crtc_state
> *pipe_config)
> u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
> const struct rc_parameters *rc_params;
> struct rc_parameters *rc = NULL;
> + int err;
> u8 i = 0;
>
> vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
> pipe_config->dsc.slice_count);
> +
> + err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
> +
> + if (err) {
> + drm_dbg_kms(&dev_priv->drm, "Slice dimension requirements not
> met\n");
> + return err;
> + }
> +
> /*
> * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb
> is 0
> * else 1
> --
> 2.25.1
