We need to read out the CDclk to calculate the DP aux divider correctly.
Signed-off-by: Jesse Barnes <[email protected]>
---
drivers/gpu/drm/i915/intel_dp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7df5085..4ac1da5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -214,6 +214,9 @@ intel_hrawclk(struct drm_device *dev)
if (IS_VALLEYVIEW(dev))
return 200;
+ if (IS_BROADWELL(dev))
+ return intel_ddi_get_cdclk_freq(dev_priv) / 1000;
+
clkcfg = I915_READ(CLKCFG);
switch (clkcfg & CLKCFG_FSB_MASK) {
case CLKCFG_FSB_400:
--
1.8.3.2
_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
