> -----Original Message-----
> From: Intel-gfx <intel-gfx-boun...@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: 21 March 2023 02:04
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 4/6] drm/i915/vrr: Tell
> intel_crtc_update_active_timings() about VRR explicitly
> 
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
> 
> In order to move VRR enable/disable to a place where it's also applicable to
> fastsets we need to be prepared to configure the pipe into non-VRR mode
> initially, and then later switch to VRR mode. To that end allow the active
> timings to be configured in non-VRR mode temporarily even when the
> crtc_state says we're going to be using VRR.
> 
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_crtc.c          |  3 ++-
>  drivers/gpu/drm/i915/display/intel_display.c       |  3 ++-
>  drivers/gpu/drm/i915/display/intel_modeset_setup.c |  3 ++-
>  drivers/gpu/drm/i915/display/intel_vblank.c        | 12 +++++++++---
>  drivers/gpu/drm/i915/display/intel_vblank.h        |  3 ++-
>  5 files changed, 17 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 41d381bbb57a..c59c4b416dcb 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -692,7 +692,8 @@ void intel_pipe_update_end(struct intel_crtc_state
> *new_crtc_state)
>        * FIXME Should be synchronized with the start of vblank somehow...
>        */
>       if (new_crtc_state->seamless_m_n &&
> intel_crtc_needs_fastset(new_crtc_state))
> -             intel_crtc_update_active_timings(new_crtc_state);
> +             intel_crtc_update_active_timings(new_crtc_state,
> +                                              new_crtc_state->vrr.enable);
> 
>       local_irq_enable();
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 5ee93824861b..fc8eafd5fa61 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6956,7 +6956,8 @@ static void intel_enable_crtc(struct
> intel_atomic_state *state,
>       if (!intel_crtc_needs_modeset(new_crtc_state))
>               return;
> 
> -     intel_crtc_update_active_timings(new_crtc_state);
> +     intel_crtc_update_active_timings(new_crtc_state,
> +                                      new_crtc_state->vrr.enable);
> 
>       dev_priv->display.funcs.display->crtc_enable(state, crtc);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index 4558d02641fe..64d12a13887d 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -560,7 +560,8 @@ static void intel_modeset_readout_hw_state(struct
> drm_i915_private *i915)
>                        */
>                       crtc_state->inherited = true;
> 
> -                     intel_crtc_update_active_timings(crtc_state);
> +                     intel_crtc_update_active_timings(crtc_state,
> +                                                      crtc_state-
> >vrr.enable);
> 
>                       intel_crtc_copy_hw_to_uapi_state(crtc_state);
>               }
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c
> b/drivers/gpu/drm/i915/display/intel_vblank.c
> index f8bf9810527d..2e4f7de199d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -488,21 +488,27 @@ static int intel_crtc_scanline_offset(const struct
> intel_crtc_state *crtc_state)
>       }
>  }
> 
> -void intel_crtc_update_active_timings(const struct intel_crtc_state
> *crtc_state)
> +void intel_crtc_update_active_timings(const struct intel_crtc_state
> *crtc_state,
> +                                   bool vrr_enable)
>  {
>       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>       struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +     u8 mode_flags = crtc_state->mode_flags;
>       struct drm_display_mode adjusted_mode;
>       int vmax_vblank_start = 0;
>       unsigned long irqflags;
> 
>       drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode);
> 
> -     if (crtc_state->vrr.enable) {
> +     if (vrr_enable) {
> +             drm_WARN_ON(&i915->drm, (mode_flags &
> I915_MODE_FLAG_VRR) == 0);
> +
>               adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;
>               adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;
>               adjusted_mode.crtc_vblank_start =
> intel_vrr_vmin_vblank_start(crtc_state);
>               vmax_vblank_start =
> intel_vrr_vmax_vblank_start(crtc_state);
> +     } else {
> +             mode_flags &= ~I915_MODE_FLAG_VRR;
>       }
> 
>       /*
> @@ -524,7 +530,7 @@ void intel_crtc_update_active_timings(const struct
> intel_crtc_state *crtc_state)
> 
>       crtc->vmax_vblank_start = vmax_vblank_start;
> 
> -     crtc->mode_flags = crtc_state->mode_flags;
> +     crtc->mode_flags = mode_flags;
> 
>       crtc->scanline_offset = intel_crtc_scanline_offset(crtc_state);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h
> b/drivers/gpu/drm/i915/display/intel_vblank.h
> index 0884db7e76ae..08e706b29149 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.h
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.h
> @@ -20,6 +20,7 @@ bool intel_crtc_get_vblank_timestamp(struct drm_crtc
> *crtc, int *max_error,  int intel_get_crtc_scanline(struct intel_crtc *crtc); 
>  void
> intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc);  void
> intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc); -void
> intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state);
> +void intel_crtc_update_active_timings(const struct intel_crtc_state
> *crtc_state,
> +                                   bool vrr_enable);
> 
>  #endif /* __INTEL_VBLANK_H__ */
> --
> 2.39.2

changes LGTM. 
Thanks
 
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com>

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