[Intel-gfx] [PATCH v2 06/13] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA

[Mika Kahola]

Use MPLLA for DP2.0 rates 10G and 20G, when ssc is enabled.

v2: Fix typo in commit message (Animesh)

Reviewed-by: Radhakrishna Sripada <radhakrishna.srip...@intel.com>
Reviewed-by: Arun R Murthy <arun.r.mur...@intel.com>
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c 
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 5409be0d5812..63d63c23647e 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2349,8 +2349,11 @@ static void intel_program_port_clock_ctl(struct 
intel_encoder *encoder,
                val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
 
        /* TODO: HDMI FRL */
-       /* TODO: DP2.0 10G and 20G rates enable MPLLA*/
-       val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 
0;
+       /* DP2.0 10G and 20G rates enable MPLLA*/
+       if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 
2000000)
+               val |= crtc_state->cx0pll_state.ssc_enabled ? 
XELPDP_SSC_ENABLE_PLLA : 0;
+       else
+               val |= crtc_state->cx0pll_state.ssc_enabled ? 
XELPDP_SSC_ENABLE_PLLB : 0;
 
        intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
                     XELPDP_LANE1_PHY_CLOCK_SELECT | 
XELPDP_FORWARD_CLOCK_UNGATE |
-- 
2.34.1