On Wed, Jan 22, 2014 at 09:15:07AM +0530, [email protected] wrote:
> From: Akash Goel <[email protected]>
>
> Modified programming of following 2 regs in Render ring initialisation fn.
> 1. GFX_MODE_GEN7 (Enabling TLB invalidate)
> 2. MI_MODE (Enabling MI Flush)
>
> Signed-off-by: Akash Goel <[email protected]>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 19 ++++++++++++++-----
> 1 file changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index e8ec536..8b99df2 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -563,7 +563,9 @@ static int init_render_ring(struct intel_ring_buffer
> *ring)
> int ret = init_ring_common(ring);
>
> if (INTEL_INFO(dev)->gen > 3)
> - I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
> + if (!IS_VALLEYVIEW(dev))
> + I915_WRITE(MI_MODE,
> + _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
BSpec says this should be enabled for everything before IVB. So based on
that the condition should just be 'if (gen > 3 && gen < 7)'
>
> /* We need to disable the AsyncFlip performance optimisations in order
> * to use MI_WAIT_FOR_EVENT within the CS. It should already be
> @@ -579,10 +581,17 @@ static int init_render_ring(struct intel_ring_buffer
> *ring)
> I915_WRITE(GFX_MODE,
> _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
>
> - if (IS_GEN7(dev))
> - I915_WRITE(GFX_MODE_GEN7,
> - _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
> - _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
> + if (IS_GEN7(dev)) {
> + if (IS_VALLEYVIEW(dev)) {
> + I915_WRITE(GFX_MODE_GEN7,
> + _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
> + I915_WRITE(MI_MODE, I915_READ(MI_MODE) |
> + _MASKED_BIT_ENABLE(MI_FLUSH_ENABLE));
Why do we need to enable MI_FLUSH, and why only for VLV?
> + } else
> + I915_WRITE(GFX_MODE_GEN7,
> + _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
> + _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
> + }
According to BSpec the GFX_TLB_INVALIDATE_ALWAYS bit only exists on SNB.
So it would we should just drop it here.
>
> if (INTEL_INFO(dev)->gen >= 5) {
> ret = init_pipe_control(ring);
> --
> 1.8.5.2
>
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--
Ville Syrjälä
Intel OTC
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