Use computed C20 HDMI TMDS pixel clocks to support 25.175MHz to 594000MHz modes. Add 16 Bit mask operators to support C20 phy programming.
v2: checkpatch fixes BSPEC: 64568 Cc: Imre Deak <[email protected]> Cc: Mika Kahola <[email protected]> Cc: Radhakrishna Sripada <[email protected]> Cc: Gustavo Sousa <[email protected]> Signed-off-by: Clint Taylor <[email protected]> Clint Taylor (2): drm/i915: Add 16bit register/mask operators drm/i915/hdmi: C20 computed PLL frequencies drivers/gpu/drm/i915/display/intel_cx0_phy.c | 89 +++++++++++++++++-- .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 53 +++++++++++ drivers/gpu/drm/i915/i915_reg_defs.h | 48 ++++++++++ 3 files changed, 184 insertions(+), 6 deletions(-) -- 2.25.1
