Re: [Intel-gfx] [PATCH] drm/i915/gt: Remove incorrect hard coded cache coherrency setting

[Dong, Zhanjun]

Resend to restart the CI,

https://patchwork.freedesktop.org/series/119485/

Was stuck.


Regards,

Zhanjun

On 2023-06-22 11:26 a.m., Zhanjun Dong wrote:

The previouse i915_gem_object_create_internal already set it with proper
value before function return. This hard coded setting is incorrect for
platforms like MTL, thus need to be removed.

Signed-off-by: Zhanjun Dong <zhanjun.d...@intel.com>
---
  drivers/gpu/drm/i915/gt/intel_timeline.c | 2 --
  1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c 
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index b9640212d659..693d18e14b00 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -26,8 +26,6 @@ static struct i915_vma *hwsp_alloc(struct intel_gt *gt)
        if (IS_ERR(obj))
                return ERR_CAST(obj);

- i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);

-
        vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
        if (IS_ERR(vma))
                i915_gem_object_put(obj);