> -----Original Message-----
> From: Murthy, Arun R <[email protected]>
> Sent: Friday, July 14, 2023 10:18 AM
> To: Manna, Animesh <[email protected]>; intel-
> [email protected]
> Subject: RE: [Intel-gfx] [PATCH 4/4] drm/i915/panelreplay: enable/disable
> panel replay
>
>
>
> > -----Original Message-----
> > From: Intel-gfx <[email protected]> On Behalf Of
> > Animesh Manna
> > Sent: Thursday, November 10, 2022 8:33 PM
> > To: [email protected]
> > Subject: [Intel-gfx] [PATCH 4/4] drm/i915/panelreplay: enable/disable
> panel
> > replay
> >
> > TRANS_DP2_CTL register is programmed to enable panel replay from
> source
> > and sink is enabled through panel replay dpcd configuration address.
> >
> > Note: Currently enabled full-screen live active frame update mode of panel
> > replay. Panel replay also can be enabled in selective update mode which
> will
> > be enabled in a incremental approach.
> >
> > Cc: Jouni Högander <[email protected]>
> > Signed-off-by: Animesh Manna <[email protected]>
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 30 ++++++++++++++++++++----
> > 1 file changed, 26 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 50394143c798..b6406c334316 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -395,8 +395,14 @@ static void intel_psr_enable_sink(struct intel_dp
> > *intel_dp)
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > u8 dpcd_val = DP_PSR_ENABLE;
> >
> > - /* Enable ALPM at sink for psr2 */
> > + if (intel_dp->psr.enabled && IS_PANEL_REPLAY(intel_dp)) {
> > + drm_dp_dpcd_writeb(&intel_dp->aux,
> > PANEL_REPLAY_CONFIG,
> > + DP_PANEL_REPLAY_ENABLE);
> > + return;
> > + }
> > +
> > if (intel_dp->psr.psr2_enabled) {
> > + /* Enable ALPM at sink for psr2 */
> > drm_dp_dpcd_writeb(&intel_dp->aux,
> > DP_RECEIVER_ALPM_CONFIG,
> > DP_ALPM_ENABLE |
> >
> > DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
> > @@ -526,6 +532,17 @@ static u32 intel_psr2_get_tp_time(struct intel_dp
> > *intel_dp)
> > return val;
> > }
> >
> > +static void dg2_activate_panel_replay(struct intel_dp *intel_dp) {
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > + intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp-
> > >psr.transcoder),
> > +
> > ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE);
> > +
> Can intel_de_rmw() be used, just to ensure that no other bits are updated.
Agree, will update in next version.
Regards,
Animesh
>
> Thanks and Regards,
> Arun R Murthy
> --------------------
>
> > + intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder),
> > 0,
> > + TRANS_DP2_PANEL_REPLAY_ENABLE);
> > +}
> > +
> > static void hsw_activate_psr2(struct intel_dp *intel_dp) {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -
> > 1101,8 +1118,10 @@ static void intel_psr_activate(struct intel_dp
> *intel_dp)
> > drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
> > lockdep_assert_held(&intel_dp->psr.lock);
> >
> > - /* psr1 and psr2 are mutually exclusive.*/
> > - if (intel_dp->psr.psr2_enabled)
> > + /* psr1, psr2 and panel-replay are mutually exclusive.*/
> > + if (intel_dp->psr.enabled && IS_PANEL_REPLAY(intel_dp))
> > + dg2_activate_panel_replay(intel_dp);
> > + else if (intel_dp->psr.psr2_enabled)
> > hsw_activate_psr2(intel_dp);
> > else
> > hsw_activate_psr1(intel_dp);
> > @@ -1300,7 +1319,10 @@ static void intel_psr_exit(struct intel_dp
> > *intel_dp)
> > return;
> > }
> >
> > - if (intel_dp->psr.psr2_enabled) {
> > + if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
> > + intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp-
> > >psr.transcoder),
> > + TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
> > + } else if (intel_dp->psr.psr2_enabled) {
> > tgl_disallow_dc3co_on_psr2_exit(intel_dp);
> > val = intel_de_read(dev_priv,
> > EDP_PSR2_CTL(intel_dp->psr.transcoder));
> > --
> > 2.29.0
