[Intel-gfx] [PATCH v7 7/9] drm/i915/gt: Ensure memory quiesced before invalidation for all engines

[Andi Shyti]

Commit af9e423a8aae ("drm/i915/gt: Ensure memory quiesced before
invalidation") has made sure that the memory is quiesced before
invalidating the AUX CCS table. Do it for all the other engines
and not just RCS.

Signed-off-by: Andi Shyti <andi.sh...@linux.intel.com>
Cc: Jonathan Cavitt <jonathan.cav...@intel.com>
Cc: Matt Roper <matthew.d.ro...@intel.com>
Cc: <sta...@vger.kernel.org> # v5.8+
---
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 36 ++++++++++++++++--------
 1 file changed, 25 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 202d6ff8b5264..b6dd22eb2d9b2 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -316,26 +316,40 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 
mode)
 int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
 {
        intel_engine_mask_t aux_inv = 0;
-       u32 cmd, *cs;
+       u32 cmd_flush = 0;
+       u32 cmd = 4;
+       u32 *cs;
 
-       cmd = 4;
-       if (mode & EMIT_INVALIDATE) {
+       if (mode & EMIT_INVALIDATE)
                cmd += 2;
 
-               if (HAS_AUX_CCS(rq->engine->i915) &&
-                   (rq->engine->class == VIDEO_DECODE_CLASS ||
-                    rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) {
-                       aux_inv = rq->engine->mask &
-                               ~GENMASK(_BCS(I915_MAX_BCS - 1), BCS0);
-                       if (aux_inv)
-                               cmd += 4;
-               }
+       if (HAS_AUX_CCS(rq->engine->i915))
+               aux_inv = rq->engine->mask &
+                         ~GENMASK(_BCS(I915_MAX_BCS - 1), BCS0);
+
+       /*
+        * On Aux CCS platforms the invalidation of the Aux
+        * table requires quiescing memory traffic beforehand
+        */
+       if (aux_inv) {
+               cmd += 4; /* for the AUX invalidation */
+               cmd += 2; /* for the engine quiescing */
+
+               cmd_flush = MI_FLUSH_DW;
+
+               if (rq->engine->class == COPY_ENGINE_CLASS)
+                       cmd_flush |= MI_FLUSH_DW_CCS;
        }
 
        cs = intel_ring_begin(rq, cmd);
        if (IS_ERR(cs))
                return PTR_ERR(cs);
 
+       if (cmd_flush) {
+               *cs++ = cmd_flush;
+               *cs++ = 0;
+       }
+
        if (mode & EMIT_INVALIDATE)
                *cs++ = preparser_disable(true);
 
-- 
2.40.1