On Wed, Aug 16, 2023 at 12:16:25PM +0530, Kalvala, Haridhar wrote:
>
> On 8/11/2023 5:16 AM, Matt Roper wrote:
> > We don't really need a feature flag for has_4tile since there's a
> > well-defined cutover point (DG2) at which all new platforms started
> > using Tile4 as their Y-major tiling layout. The GT side of the code
> > already handles Tile4 vs legacy TileY with checks on the IP version
> > rather than looking at the feature flag, and we can simplify the display
> > code similarly (which will also make it more self-contained for re-use
> > in the Xe driver).
>
> Hi Matt,
>
> Looks good to me.
>
> > Signed-off-by: Matt Roper <[email protected]>
> > ---
> > drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
> > drivers/gpu/drm/i915/i915_drv.h | 1 -
> > drivers/gpu/drm/i915/i915_pci.c | 1 -
> > drivers/gpu/drm/i915/intel_device_info.h | 1 -
> > 4 files changed, 1 insertion(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> > b/drivers/gpu/drm/i915/display/intel_display_device.h
> > index 215e682bd8b7..eb630a946343 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> > @@ -32,6 +32,7 @@ struct drm_printer;
> > func(overlay_needs_physical); \
> > func(supports_tv);
> > +#define HAS_4TILE(i915) (IS_DG2(i915) ||
> > DISPLAY_VER(i915) >= 14)
> is this tab space aligned with below lines ?
Yes, it's aligned with the code below. But if you're just reading the
diff, the extra column added for the '+' at the beginning of the line
throws off the spacing.
Matt
> > #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
> > #define HAS_CDCLK_CRAWL(i915)
> > (DISPLAY_INFO(i915)->has_cdclk_crawl)
> > #define HAS_CDCLK_SQUASH(i915)
> > (DISPLAY_INFO(i915)->has_cdclk_squash)
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 7a8ce7239bc9..4c6852f0a61c 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -737,7 +737,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > #define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7)
> > #define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc)
> > -#define HAS_4TILE(i915) (INTEL_INFO(i915)->has_4tile)
> > #define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop)
> > #define HAS_EDRAM(i915) ((i915)->edram_size_mb)
> > #define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6)
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c
> > index fcacdc21643c..df7c261410f7 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -713,7 +713,6 @@ static const struct intel_device_info adl_p_info = {
> > .has_3d_pipeline = 1, \
> > .has_64bit_reloc = 1, \
> > .has_flat_ccs = 1, \
> > - .has_4tile = 1, \
> > .has_global_mocs = 1, \
> > .has_gt_uc = 1, \
> > .has_llc = 1, \
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > b/drivers/gpu/drm/i915/intel_device_info.h
> > index dbfe6443457b..19d120728ff1 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -150,7 +150,6 @@ enum intel_ppgtt_type {
> > func(gpu_reset_clobbers_display); \
> > func(has_reset_engine); \
> > func(has_3d_pipeline); \
> > - func(has_4tile); \
> > func(has_flat_ccs); \
> > func(has_global_mocs); \
> > func(has_gmd_id); \
>
> --
> Regards,
> Haridhar Kalvala
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
