[Intel-gfx] [PATCH v3] drm/i915/display: Reset message bus after each read/write operation

[Mika Kahola]

Every know and then we receive the following error when running
for example IGT test kms_flip.

[drm] *ERROR* PHY G Read 0d80 failed after 3 retries.
[drm] *ERROR* PHY G Write 0d81 failed after 3 retries.

Since the error is sporadic in nature, the patch proposes
to reset the message bus after every successful or unsuccessful
read or write operation.

v2: Add FIXME's to indicate the experimental nature of
    this workaround (Rodrigo)
v3: Dropping the additional delay as moving reset to *_read_once()
    and *_write_once() functions seem unnecessary delay

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c 
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 6e6a1818071e..9e24f820d4cf 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -206,6 +206,13 @@ static int __intel_cx0_read_once(struct drm_i915_private 
*i915, enum port port,
 
        intel_clear_response_ready_flag(i915, port, lane);
 
+       /*
+        * FIXME: Workaround to let HW to settle
+        * down and let the message bus to end up
+        * in a known state
+        */
+       intel_cx0_bus_reset(i915, port, lane);
+
        return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val);
 }
 
@@ -285,6 +292,13 @@ static int __intel_cx0_write_once(struct drm_i915_private 
*i915, enum port port,
 
        intel_clear_response_ready_flag(i915, port, lane);
 
+       /*
+        * FIXME: Workaround to let HW to settle
+        * down and let the message bus to end up
+        * in a known state
+        */
+       intel_cx0_bus_reset(i915, port, lane);
+
        return 0;
 }
 
-- 
2.34.1