On Fri, 03 Nov 2023, Vinod Govindapillai <[email protected]> wrote: > Implement the alternate WA for the underruns when both PSR2 > and FBC is enabled.
But we don't enable FBC when PSR2 is enabled, for display 12+. See intel_fbc.c line 1200 or so. BR, Jani. > > Signed-off-by: Vinod Govindapillai <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_fbc.c | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c > b/drivers/gpu/drm/i915/display/intel_fbc.c > index bde12fe62275..b9cd92a997cd 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -608,6 +608,7 @@ static u32 ivb_dpfc_ctl(struct intel_fbc *fbc) > static void ivb_fbc_activate(struct intel_fbc *fbc) > { > struct drm_i915_private *i915 = fbc->i915; > + u32 dpfc_ctl; > > if (DISPLAY_VER(i915) >= 10) > glk_fbc_program_cfb_stride(fbc); > @@ -617,8 +618,17 @@ static void ivb_fbc_activate(struct intel_fbc *fbc) > if (intel_gt_support_legacy_fencing(to_gt(i915))) > snb_fbc_program_fence(fbc); > > + /* > + * Alternate WA for HW bug with PSR2 + FBC. > + * 1.Write FBC_CTL with Plane binding set correctly with FBC enable = 0 > + * 2.Write FBC_CTL with Plane binding set correctly with FBC enable = 1 > + */ > + dpfc_ctl = ivb_dpfc_ctl(fbc); > + if (DISPLAY_VER(i915) >= 20) > + intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); > + > intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), > - DPFC_CTL_EN | ivb_dpfc_ctl(fbc)); > + DPFC_CTL_EN | dpfc_ctl); > } > > static bool ivb_fbc_is_compressing(struct intel_fbc *fbc) -- Jani Nikula, Intel
