Moving intel_c20pll_readout_hw_state() for better place
to better suit for upcoming changes.
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 116 +++++++++----------
1 file changed, 58 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 5fbec5784b83..2e6412fc2258 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2123,64 +2123,6 @@ static bool intel_c20_use_mplla(u32 clock)
return false;
}
-static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
- struct intel_c20pll_state *pll_state)
-{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- bool cntx;
- intel_wakeref_t wakeref;
- int i;
-
- wakeref = intel_cx0_phy_transaction_begin(encoder);
-
- /* 1. Read current context selection */
- cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0,
PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;
-
- /* Read Tx configuration */
- for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
- if (cntx)
- pll_state->tx[i] = intel_c20_sram_read(i915,
encoder->port, INTEL_CX0_LANE0,
-
PHY_C20_B_TX_CNTX_CFG(i));
- else
- pll_state->tx[i] = intel_c20_sram_read(i915,
encoder->port, INTEL_CX0_LANE0,
-
PHY_C20_A_TX_CNTX_CFG(i));
- }
-
- /* Read common configuration */
- for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
- if (cntx)
- pll_state->cmn[i] = intel_c20_sram_read(i915,
encoder->port, INTEL_CX0_LANE0,
-
PHY_C20_B_CMN_CNTX_CFG(i));
- else
- pll_state->cmn[i] = intel_c20_sram_read(i915,
encoder->port, INTEL_CX0_LANE0,
-
PHY_C20_A_CMN_CNTX_CFG(i));
- }
-
- if (pll_state->tx[0] & C20_PHY_USE_MPLLB) {
- /* MPLLB configuration */
- for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
- if (cntx)
- pll_state->mpllb[i] = intel_c20_sram_read(i915,
encoder->port, INTEL_CX0_LANE0,
-
PHY_C20_B_MPLLB_CNTX_CFG(i));
- else
- pll_state->mpllb[i] = intel_c20_sram_read(i915,
encoder->port, INTEL_CX0_LANE0,
-
PHY_C20_A_MPLLB_CNTX_CFG(i));
- }
- } else {
- /* MPLLA configuration */
- for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
- if (cntx)
- pll_state->mplla[i] = intel_c20_sram_read(i915,
encoder->port, INTEL_CX0_LANE0,
-
PHY_C20_B_MPLLA_CNTX_CFG(i));
- else
- pll_state->mplla[i] = intel_c20_sram_read(i915,
encoder->port, INTEL_CX0_LANE0,
-
PHY_C20_A_MPLLA_CNTX_CFG(i));
- }
- }
-
- intel_cx0_phy_transaction_end(encoder, wakeref);
-}
-
void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
const struct intel_c20pll_state *hw_state)
{
@@ -2503,6 +2445,64 @@ static void intel_program_port_clock_ctl(struct
intel_encoder *encoder,
XELPDP_SSC_ENABLE_PLLB, val);
}
+static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
+ struct intel_c20pll_state *pll_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ bool cntx;
+ intel_wakeref_t wakeref;
+ int i;
+
+ wakeref = intel_cx0_phy_transaction_begin(encoder);
+
+ /* 1. Read current context selection */
+ cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0,
PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;
+
+ /* Read Tx configuration */
+ for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
+ if (cntx)
+ pll_state->tx[i] = intel_c20_sram_read(i915,
encoder->port, INTEL_CX0_LANE0,
+
PHY_C20_B_TX_CNTX_CFG(i));
+ else
+ pll_state->tx[i] = intel_c20_sram_read(i915,
encoder->port, INTEL_CX0_LANE0,
+
PHY_C20_A_TX_CNTX_CFG(i));
+ }
+
+ /* Read common configuration */
+ for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
+ if (cntx)
+ pll_state->cmn[i] = intel_c20_sram_read(i915,
encoder->port, INTEL_CX0_LANE0,
+
PHY_C20_B_CMN_CNTX_CFG(i));
+ else
+ pll_state->cmn[i] = intel_c20_sram_read(i915,
encoder->port, INTEL_CX0_LANE0,
+
PHY_C20_A_CMN_CNTX_CFG(i));
+ }
+
+ if (pll_state->tx[0] & C20_PHY_USE_MPLLB) {
+ /* MPLLB configuration */
+ for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
+ if (cntx)
+ pll_state->mpllb[i] = intel_c20_sram_read(i915,
encoder->port, INTEL_CX0_LANE0,
+
PHY_C20_B_MPLLB_CNTX_CFG(i));
+ else
+ pll_state->mpllb[i] = intel_c20_sram_read(i915,
encoder->port, INTEL_CX0_LANE0,
+
PHY_C20_A_MPLLB_CNTX_CFG(i));
+ }
+ } else {
+ /* MPLLA configuration */
+ for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
+ if (cntx)
+ pll_state->mplla[i] = intel_c20_sram_read(i915,
encoder->port, INTEL_CX0_LANE0,
+
PHY_C20_B_MPLLA_CNTX_CFG(i));
+ else
+ pll_state->mplla[i] = intel_c20_sram_read(i915,
encoder->port, INTEL_CX0_LANE0,
+
PHY_C20_A_MPLLA_CNTX_CFG(i));
+ }
+ }
+
+ intel_cx0_phy_transaction_end(encoder, wakeref);
+}
+
static u32 intel_cx0_get_powerdown_update(u8 lane_mask)
{
u32 val = 0;
--
2.34.1
