On Tue, 19 Dec 2023, Jouni Högander <jouni.hogan...@intel.com> wrote:
Commit message goes here. > Signed-off-by: Jouni Högander <jouni.hogan...@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr_regs.h | 103 ++++++++++++++++++ > 1 file changed, 103 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h > b/drivers/gpu/drm/i915/display/intel_psr_regs.h > index efe4306b37e0..9410a43e901b 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > @@ -290,4 +290,107 @@ > _SEL_FETCH_PLANE_OFFSET_1_A - > \ > _SEL_FETCH_PLANE_BASE_1_A) > > +#define _ALPM_CTL_A 0x60950 > +#define ALPM_CTL(tran) _MMIO_TRANS2(tran, _ALPM_CTL_A) > +#define ALPM_CTL_ALPM_ENABLE BIT(31) > +#define ALPM_CTL_ALPM_AUX_LESS_ENABLE BIT(30) > +#define ALPM_CTL_LOBF_ENABLE BIT(29) > +#define ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE BIT(28) > +#define ALPM_CTL_KEEP_FEC_ENABLE_FOR_AUX_WAKE_SLEEP BIT(27) > +#define ALPM_CTL_RESTORE_OCCURED BIT(26) > +#define ALPM_CTL_RESTORE_TO_SLEEP BIT(25) > +#define ALPM_CTL_RESTORE_TO_DEEP_SLEEP BIT(24) Please use REG_BIT() throughout. > +#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK REG_GENMASK(23, > 21) > +#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS > REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 0) > +#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_128_SYMBOLS > REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 1) > +#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_256_SYMBOLS > REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 2) > +#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_512_SYMBOLS > REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 3) > +#define ALPM_CTL_AUX_WAKE_SLEEP_HOLD_ENABLE BIT(20) > +#define ALPM_CTL_ALPM_ENTRY_CHECK_MASK REG_GENMASK(19, > 16) > +#define ALPM_CTL_ALPM_ENTRY_CHECK(val) > REG_FIELD_PREP(ALPM_CTL_ALPM_ENTRY_CHECK_MASK, val) > +#define ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK REG_GENMASK(13, > 8) > +#define ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES 5 > +#define ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines) > REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK, (lines) - > ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES) > +#define ALPM_CTL_AUX_LESS_WAKE_TIME_MASK REG_GENMASK(5, 0) > +#define ALPM_CTL_AUX_LESS_WAKE_TIME(val) > REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val) > + > +#define _ALPM_CTL2_A 0x60950 > +#define ALPM_CTL2(tran) _MMIO_TRANS2(tran, _ALPM_CTL2_A) > +#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK REG_GENMASK(28, > 24) > +#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val) > REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val) > +#define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK REG_GENMASK(19, > 16) > +#define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION(val) > REG_FIELD_PREP(ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK, val) > +#define ALPM_CTL2_NUMBER_OF_LTTPR_MASK > REG_GENMASK(15, 12) > +#define ALPM_CTL2_NUMBER_OF_LTTPR(val) > REG_FIELD_PREP(ALPM_CTL2_NUMBER_OF_LTTPR_MASK, val) > +#define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK > REG_GENMASK(10, 8) > +#define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME(val) > REG_FIELD_PREP(ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK, val) > +#define ALPM_CTL2_FEC_DECODE_EN_POSITION_AFTER_WAKE_SR BIT(4) > +#define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK > REG_GENMASK(2, 0) > +#define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val) > REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val) > + > +#define _PORT_ALPM_CTL_A 0x16fa2c > +#define PORT_ALPM_CTL(tran) _MMIO_TRANS2(tran, > _PORT_ALPM_CTL_A) > +#define PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE BIT(31) > +#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(23, 20) > +#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val) > REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val) > +#define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK REG_GENMASK(19, 16) > +#define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(val) > REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK, val) > +#define PORT_ALPM_CTL_SILENCE_PERIOD_MASK REG_GENMASK(7, 0) > +#define PORT_ALPM_CTL_SILENCE_PERIOD(val) > REG_FIELD_PREP(PORT_ALPM_CTL_SILENCE_PERIOD_MASK, val) > + > +#define _PORT_ALPM_LFPS_CTL_A 0x16fa30 > +#define PORT_ALPM_LFPS_CTL(tran) > _MMIO_TRANS2(tran, _PORT_ALPM_LFPS_CTL_A) > +#define PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY BIT(31) > +#define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK REG_GENMASK(27, > 24) > +#define ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES 5 > +#define ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines) > REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK, (lines) - > ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES) > +#define ALPM_CTL_AUX_LESS_WAKE_TIME_MASK REG_GENMASK(5, 0) > +#define ALPM_CTL_AUX_LESS_WAKE_TIME(val) > REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val) > + > +#define _ALPM_CTL2_A 0x60950 > +#define ALPM_CTL2(tran) _MMIO_TRANS2(tran, _ALPM_CTL2_A) > +#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK REG_GENMASK(28, > 24) > +#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val) > REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val) > +#define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK REG_GENMASK(19, > 16) > +#define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION(val) > REG_FIELD_PREP(ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK, val) > +#define ALPM_CTL2_NUMBER_OF_LTTPR_MASK > REG_GENMASK(15, 12) > +#define ALPM_CTL2_NUMBER_OF_LTTPR(val) > REG_FIELD_PREP(ALPM_CTL2_NUMBER_OF_LTTPR_MASK, val) > +#define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK > REG_GENMASK(10, 8) > +#define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME(val) > REG_FIELD_PREP(ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK, val) > +#define ALPM_CTL2_FEC_DECODE_EN_POSITION_AFTER_WAKE_SR BIT(4) > +#define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK > REG_GENMASK(2, 0) > +#define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val) > REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val) > + > +#define _PORT_ALPM_CTL_A 0x16fa2c > +#define PORT_ALPM_CTL(tran) _MMIO_TRANS2(tran, > _PORT_ALPM_CTL_A) > +#define ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES 5 > +#define ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines) > REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK, (lines) - > ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES) > +#define ALPM_CTL_AUX_LESS_WAKE_TIME_MASK REG_GENMASK(5, 0) > +#define ALPM_CTL_AUX_LESS_WAKE_TIME(val) > REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val) > + > +#define _ALPM_CTL2_A 0x60950 > +#define ALPM_CTL2(tran) _MMIO_TRANS2(tran, _ALPM_CTL2_A) > +#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK REG_GENMASK(28, > 24) > +#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val) > REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val) > +#define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK REG_GENMASK(19, > 16) > +#define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION(val) > REG_FIELD_PREP(ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK, val) > +#define ALPM_CTL2_NUMBER_OF_LTTPR_MASK > REG_GENMASK(15, 12) > +#define ALPM_CTL2_NUMBER_OF_LTTPR(val) > REG_FIELD_PREP(ALPM_CTL2_NUMBER_OF_LTTPR_MASK, val) > +#define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK > REG_GENMASK(10, 8) > +#define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME(val) > REG_FIELD_PREP(ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK, val) > +#define ALPM_CTL2_FEC_DECODE_EN_POSITION_AFTER_WAKE_SR BIT(4) > +#define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK > REG_GENMASK(2, 0) > +#define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val) > REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val) > + > +#define _PORT_ALPM_CTL_A 0x16fa2c > +#define PORT_ALPM_CTL(tran) _MMIO_TRANS2(tran, > _PORT_ALPM_CTL_A) > +#define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN 7 > +#define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(val) > REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK, (val) - > PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN) > +#define PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK REG_GENMASK(20, > 16) > +#define PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val) > REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val) > +#define PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK > REG_GENMASK(12, 8) > +#define PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val) > REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val) > +#define PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK > REG_GENMASK(4, 0) > +#define PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val) > REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val) > + > #endif /* __INTEL_PSR_REGS_H__ */ -- Jani Nikula, Intel
