Add pll selection check for C20 as well as
clock state verification0. We have been relying
on sw state to select A or B pll's. This is incorrect
as the hw might see this selection differently. This
patch fixes this shortcoming by reading pll selection
for both sw and hw states and compares if these two
selections match.
While at it, cleanup mpllb selection by removing intel_c20_use_mplla()
function as redundant.
Fixes: 59be90248b42 ("drm/i915/mtl: C20 state verification")
v2: reword commit message and include fix to a
original commit (Imre)
Compare pll selection (Jani)
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
Mika Kahola (3):
drm/i915/display: Fix C20 pll selection for state verification
drm/i915/display: Store hw clock for C20
drm/i915/display: Cleanup mplla/mpllb selection
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 153 ++++++++++---------
1 file changed, 78 insertions(+), 75 deletions(-)
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2.34.1
