On Mon, Jan 22, 2024 at 08:50:46AM +0000, Kandpal, Suraj wrote:
> > Subject: [PATCH] drm/i915: Try to preserve the current shared_dpll for
> > fastset
> > on type-c ports
> >
> > From: Ville Syrjälä <[email protected]>
> >
> > Currently icl_compute_tc_phy_dplls() assumes that the active PLL will be the
> > TC PLL (as opposed to the TBT PLL). The actual PLL will be selected during
> > the
> > modeset enable sequence, but we need to put *something* into the
> > crtc_state->shared_dpll already during compute_config().
> >
> > The downside of assuming one PLL or the other is that we'll fail to fastset
> > if the
> > assumption doesn't match what was in use previously. So let's instead keep
> > the same PLL that was in use previously (assuming there was one). This
> > should
> > allow fastset to work again when using TBT PLL, at least in the steady
> > state.
> >
> > Now, assuming we want keep the same PLL may not be entirely correct either.
> > But we should be covered by the typ-c link reset handling which will force
> > a full
>
> Small typo *type-c
>
> > modeset by flagging connectors_changed=true which means the resulting
> > modeset can't be converted into a fastset even if the full crtc state looks
> > identical.
> >
> > Cc: Imre Deak <[email protected]>
> > Cc: Suraj Kandpal <[email protected]>
> > Signed-off-by: Ville Syrjälä <[email protected]>
>
> LGTM.
> Signed-off-by: Suraj Kandpal <[email protected]>
I took that as Reviewed-by and pushed to drm-intel-next. Thanks.
>
> > ---
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 +++++++-
> > 1 file changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index ef57dad1a9cb..1008e18177c9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -3308,6 +3308,8 @@ static int icl_compute_tc_phy_dplls(struct
> > intel_atomic_state *state,
> > struct drm_i915_private *i915 = to_i915(state->base.dev);
> > struct intel_crtc_state *crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > + const struct intel_crtc_state *old_crtc_state =
> > + intel_atomic_get_old_crtc_state(state, crtc);
> > struct icl_port_dpll *port_dpll =
> > &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> > struct skl_wrpll_params pll_params = {}; @@ -3326,7 +3328,11 @@
> > static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
> > return ret;
> >
> > /* this is mainly for the fastset check */
> > - icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
> > + if (old_crtc_state->shared_dpll &&
> > + old_crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL)
> > + icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
> > + else
> > + icl_set_active_port_dpll(crtc_state,
> > ICL_PORT_DPLL_MG_PHY);
> >
> > crtc_state->port_clock = icl_ddi_mg_pll_get_freq(i915, NULL,
> > &port_dpll-
> > >hw_state);
> > --
> > 2.41.0
>
--
Ville Syrjälä
Intel
