Driver currently limits link rate up to HBR3 in SST mode. Log a
message with monitor vendor, product id, and MSTM_CAP to
help understand what monitors are being downgraded by this limit.

Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Cc: Khaled Almahallawy <khaled.almahall...@intel.com>
Cc: Sean Paul <seanp...@chromium.org>
Signed-off-by: Charlton Lin <charlton....@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 6ece2c563c7a..0b2d6d88fd37 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2437,6 +2437,25 @@ intel_dp_compute_link_config(struct intel_encoder 
*encoder,
                                                     false,
                                                     &limits);
 
+       if (intel_dp_max_common_rate(intel_dp) > limits.max_rate) {
+               u8 mstm_cap;
+               u32 panel_id = drm_edid_get_panel_id(&intel_dp->aux.ddc);
+               char vend[4];
+               u16 product_id;
+
+               drm_dbg_kms(&i915->drm,
+                           "Limiting LR from max common rate %d to %d\n",
+                           intel_dp_max_common_rate(intel_dp), 
limits.max_rate);
+
+               drm_edid_decode_panel_id(panel_id, vend, &product_id);
+
+               if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_12 &&
+                   drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) 
== 1)
+                       drm_dbg_kms(&i915->drm,
+                                   "Manufacturer=%s Model=%x Sink 
MSTM_CAP=%x\n",
+                                   vend, product_id, mstm_cap);
+       }
+
        if (!dsc_needed) {
                /*
                 * Optimize for slow and wide for everything, because there are 
some
-- 
2.25.1

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