Increasing number of fast wake sync pulses seem to fix problems with certain PSR panels. This should be ok for other panels as well as the eDP specification allows 10...16 precharge pulses and we are still within that range.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9739 Signed-off-by: Jouni Högander <jouni.hogan...@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index 7e69be100d90..5dff1bc85d61 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -145,7 +145,7 @@ static int intel_dp_aux_sync_len(void) int intel_dp_aux_fw_sync_len(void) { - int precharge = 10; /* 10-16 */ + int precharge = 12; /* 10-16 */ int preamble = 8; return precharge + preamble; -- 2.34.1
