On Wed, Mar 13, 2024 at 03:32:21PM +0200, Jouni Högander wrote: > Increasing number of fast wake sync pulses seem to fix problems with > certain PSR panels. This should be ok for other panels as well as the eDP > specification allows 10...16 precharge pulses and we are still within that > range. > > v2: add comment explaining pulse count is increased > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9739 > Signed-off-by: Jouni Högander <jouni.hogan...@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp_aux.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c > b/drivers/gpu/drm/i915/display/intel_dp_aux.c > index 7e69be100d90..3264026454b2 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c > @@ -145,7 +145,12 @@ static int intel_dp_aux_sync_len(void) > > int intel_dp_aux_fw_sync_len(void) > { > - int precharge = 10; /* 10-16 */ > + /* > + * We faced some glitches on MTL with one PSR2 panel when using HW > + * default 18. Using 20 is fixing these problems with the panel. It is > + * still within range mentioned in eDP specification. > + */
"MTL with one PSR2 panel" is super vague. Please mention the actual machine model here. With that Acked-by: Ville Syrjälä <ville.syrj...@linux.intel.com> > + int precharge = 12; /* 10-16 */ > int preamble = 8; > > return precharge + preamble; > -- > 2.34.1 -- Ville Syrjälä Intel
