On Wed, Apr 03, 2024 at 04:52:35PM +0530, Balasubramani Vivekanandan wrote: > From: Ankit Nautiyal <[email protected]> > > This reverts commit 562f33836f519a235e5c5e71bcc723ab1faccd2f. > For BMG it seems that the VBT to DDI mapping does not follow DG1, and > DG2, but follows ADLP mapping given in Bspec:20124. > > Signed-off-by: Ankit Nautiyal <[email protected]> > Signed-off-by: Balasubramani Vivekanandan > <[email protected]>
Matches our experimental findings, so Reviewed-by: Matt Roper <[email protected]> I've pinged the internal ticket to try to get the documentation for this clarified. BTW, if you send another version of this series it might make more sense to re-order this to be after patch #20, since that's where we define which south display (i.e., "fake pch") is used on BMG. Matt > --- > drivers/gpu/drm/i915/display/intel_bios.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c > b/drivers/gpu/drm/i915/display/intel_bios.c > index 2abd2d7ceda2..03fbd6c73f3f 100644 > --- a/drivers/gpu/drm/i915/display/intel_bios.c > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > @@ -2238,15 +2238,14 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, > u8 vbt_pin) > const u8 *ddc_pin_map; > int i, n_entries; > > - if (IS_DGFX(i915)) > - return vbt_pin; > - > if (INTEL_PCH_TYPE(i915) >= PCH_MTL || IS_ALDERLAKE_P(i915)) { > ddc_pin_map = adlp_ddc_pin_map; > n_entries = ARRAY_SIZE(adlp_ddc_pin_map); > } else if (IS_ALDERLAKE_S(i915)) { > ddc_pin_map = adls_ddc_pin_map; > n_entries = ARRAY_SIZE(adls_ddc_pin_map); > + } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { > + return vbt_pin; > } else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) { > ddc_pin_map = rkl_pch_tgp_ddc_pin_map; > n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map); > -- > 2.25.1 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
