On Fri, Apr 12, 2024 at 05:52:54PM +0300, Jani Nikula wrote: > For some reason the paletter registers were missed when adding > intel_color_regs.h. Finish the job. > > Signed-off-by: Jani Nikula <[email protected]> > --- > .../gpu/drm/i915/display/intel_color_regs.h | 30 +++++++++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 30 ------------------- > 2 files changed, 30 insertions(+), 30 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h > b/drivers/gpu/drm/i915/display/intel_color_regs.h > index 9f4ae58f3e7e..969745821172 100644 > --- a/drivers/gpu/drm/i915/display/intel_color_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h > @@ -8,6 +8,36 @@ > > #include "intel_display_reg_defs.h" > > +/* > + * Palette regs > + */
Quite redundant. If we want to keep a comment then it should be adjusted to say these are for gmch platforms. > +#define _PALETTE_A 0xa000 > +#define _PALETTE_B 0xa800 > +#define _CHV_PALETTE_C 0xc000 > +/* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */ > +#define PALETTE_RED_MASK REG_GENMASK(23, 16) > +#define PALETTE_GREEN_MASK REG_GENMASK(15, 8) > +#define PALETTE_BLUE_MASK REG_GENMASK(7, 0) > +/* pre-i965 10bit interpolated mode ldw */ > +#define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16) > +#define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8) > +#define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0) > +/* pre-i965 10bit interpolated mode udw */ > +#define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22) > +#define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18) > +#define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16) > +#define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14) > +#define PALETTE_10BIT_GREEN_MANT_MASK REG_GENMASK(13, 10) > +#define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8) > +#define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6) > +#define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2) > +#define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0) > +#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + > \ > + _PICK_EVEN_2RANGES(pipe, 2, > \ > + _PALETTE_A, _PALETTE_B, > \ > + _CHV_PALETTE_C, > _CHV_PALETTE_C) + \ > + (i) * 4) > + > /* legacy palette */ and then this should be adjusted to indicate ilk+ Otherwise Reviewed-by: Ville Syrjälä <[email protected]> > #define _LGC_PALETTE_A 0x4a000 > #define _LGC_PALETTE_B 0x4a800 > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index c689bc7e2867..b74965383a56 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1700,36 +1700,6 @@ > > #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) > > -/* > - * Palette regs > - */ > -#define _PALETTE_A 0xa000 > -#define _PALETTE_B 0xa800 > -#define _CHV_PALETTE_C 0xc000 > -/* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */ > -#define PALETTE_RED_MASK REG_GENMASK(23, 16) > -#define PALETTE_GREEN_MASK REG_GENMASK(15, 8) > -#define PALETTE_BLUE_MASK REG_GENMASK(7, 0) > -/* pre-i965 10bit interpolated mode ldw */ > -#define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16) > -#define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8) > -#define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0) > -/* pre-i965 10bit interpolated mode udw */ > -#define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22) > -#define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18) > -#define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16) > -#define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14) > -#define PALETTE_10BIT_GREEN_MANT_MASK REG_GENMASK(13, 10) > -#define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8) > -#define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6) > -#define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2) > -#define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0) > -#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + > \ > - _PICK_EVEN_2RANGES(pipe, 2, > \ > - _PALETTE_A, _PALETTE_B, > \ > - _CHV_PALETTE_C, > _CHV_PALETTE_C) + \ > - (i) * 4) > - > #define PEG_BAND_GAP_DATA _MMIO(0x14d68) > > #define BXT_RP_STATE_CAP _MMIO(0x138170) > -- > 2.39.2 -- Ville Syrjälä Intel
