On Tue, 16 Apr 2024, Suraj Kandpal <suraj.kand...@intel.com> wrote:
> Disable bit 29 of SCLKGATE_DIS register around pps sequence
> when we turn panel power on.
Add blank line here.
> WA: 16023567976
> Bspec: 49304
>
Remove blank line here.
> Signed-off-by: Suraj Kandpal <suraj.kand...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_pps.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
> b/drivers/gpu/drm/i915/display/intel_pps.c
> index 3078dfac7817..a912e712ca63 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -919,6 +919,7 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> u32 pp;
> i915_reg_t pp_ctrl_reg;
> + int dis_ver = DISPLAY_VER(dev_priv);
Please don't do this. You don't see this done *anywhere* in the driver.
>
> lockdep_assert_held(&dev_priv->display.pps.mutex);
>
> @@ -948,6 +949,13 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp)
> intel_de_posting_read(dev_priv, pp_ctrl_reg);
> }
>
> + /* WA: 16023567976
For multiline comments please don't add anything after /*.
> + * Disable DPLS gating around power sequence.
> + */
> + if (dis_ver >= 12 && dis_ver <= 14)
See IS_DISPLAY_VER().
> + intel_de_rmw(dev_priv, SCLKGATE_DIS,
> + DPLS_GATING_DISABLE, 1);
> +
> pp |= PANEL_POWER_ON;
> if (!IS_IRONLAKE(dev_priv))
> pp |= PANEL_POWER_RESET;
> @@ -958,6 +966,10 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp)
> wait_panel_on(intel_dp);
> intel_dp->pps.last_power_on = jiffies;
>
> + if (dis_ver >= 12 && dis_ver <= 14)
See IS_DISPLAY_VER().
> + intel_de_rmw(dev_priv, SCLKGATE_DIS,
> + DPLS_GATING_DISABLE, 0);
> +
> if (IS_IRONLAKE(dev_priv)) {
> pp |= PANEL_POWER_RESET; /* restore panel reset bit */
> intel_de_write(dev_priv, pp_ctrl_reg, pp);
--
Jani Nikula, Intel
