On Mon, May 06, 2024 at 01:09:03PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PIPE_CRC_RES_* register macros.
>
> Signed-off-by: Jani Nikula <jani.nik...@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_irq.c | 24 ++++++++++---------
> drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++---------
> 2 files changed, 24 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
> b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index c41f058acaff..1674570dff1e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -356,7 +356,7 @@ static void hsw_pipe_crc_irq_handler(struct
> drm_i915_private *dev_priv,
> enum pipe pipe)
> {
> display_pipe_crc_irq_handler(dev_priv, pipe,
> - intel_uncore_read(&dev_priv->uncore,
> PIPE_CRC_RES_1_IVB(pipe)),
> + intel_uncore_read(&dev_priv->uncore,
> PIPE_CRC_RES_1_IVB(dev_priv, pipe)),
I believe the _IVB variants could be defined without
needing dev_priv.
But this works as well so
Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> 0, 0, 0, 0);
> }
>
> @@ -364,11 +364,11 @@ static void ivb_pipe_crc_irq_handler(struct
> drm_i915_private *dev_priv,
> enum pipe pipe)
> {
> display_pipe_crc_irq_handler(dev_priv, pipe,
> - intel_uncore_read(&dev_priv->uncore,
> PIPE_CRC_RES_1_IVB(pipe)),
> - intel_uncore_read(&dev_priv->uncore,
> PIPE_CRC_RES_2_IVB(pipe)),
> - intel_uncore_read(&dev_priv->uncore,
> PIPE_CRC_RES_3_IVB(pipe)),
> - intel_uncore_read(&dev_priv->uncore,
> PIPE_CRC_RES_4_IVB(pipe)),
> - intel_uncore_read(&dev_priv->uncore,
> PIPE_CRC_RES_5_IVB(pipe)));
> + intel_uncore_read(&dev_priv->uncore,
> PIPE_CRC_RES_1_IVB(dev_priv, pipe)),
> + intel_uncore_read(&dev_priv->uncore,
> PIPE_CRC_RES_2_IVB(dev_priv, pipe)),
> + intel_uncore_read(&dev_priv->uncore,
> PIPE_CRC_RES_3_IVB(dev_priv, pipe)),
> + intel_uncore_read(&dev_priv->uncore,
> PIPE_CRC_RES_4_IVB(dev_priv, pipe)),
> + intel_uncore_read(&dev_priv->uncore,
> PIPE_CRC_RES_5_IVB(dev_priv, pipe)));
> }
>
> static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
> @@ -377,19 +377,21 @@ static void i9xx_pipe_crc_irq_handler(struct
> drm_i915_private *dev_priv,
> u32 res1, res2;
>
> if (DISPLAY_VER(dev_priv) >= 3)
> - res1 = intel_uncore_read(&dev_priv->uncore,
> PIPE_CRC_RES_RES1_I915(pipe));
> + res1 = intel_uncore_read(&dev_priv->uncore,
> + PIPE_CRC_RES_RES1_I915(dev_priv,
> pipe));
> else
> res1 = 0;
>
> if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
> - res2 = intel_uncore_read(&dev_priv->uncore,
> PIPE_CRC_RES_RES2_G4X(pipe));
> + res2 = intel_uncore_read(&dev_priv->uncore,
> + PIPE_CRC_RES_RES2_G4X(dev_priv, pipe));
> else
> res2 = 0;
>
> display_pipe_crc_irq_handler(dev_priv, pipe,
> - intel_uncore_read(&dev_priv->uncore,
> PIPE_CRC_RES_RED(pipe)),
> - intel_uncore_read(&dev_priv->uncore,
> PIPE_CRC_RES_GREEN(pipe)),
> - intel_uncore_read(&dev_priv->uncore,
> PIPE_CRC_RES_BLUE(pipe)),
> + intel_uncore_read(&dev_priv->uncore,
> PIPE_CRC_RES_RED(dev_priv, pipe)),
> + intel_uncore_read(&dev_priv->uncore,
> PIPE_CRC_RES_GREEN(dev_priv, pipe)),
> + intel_uncore_read(&dev_priv->uncore,
> PIPE_CRC_RES_BLUE(dev_priv, pipe)),
> res1, res2);
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4525afafc79f..4a88eb9cd1f8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1138,17 +1138,17 @@
> #define _PIPE_CRC_RES_5_B_IVB 0x61074
>
> #define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe,
> _PIPE_CRC_CTL_A)
> -#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe,
> _PIPE_CRC_RES_1_A_IVB)
> -#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe,
> _PIPE_CRC_RES_2_A_IVB)
> -#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe,
> _PIPE_CRC_RES_3_A_IVB)
> -#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe,
> _PIPE_CRC_RES_4_A_IVB)
> -#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe,
> _PIPE_CRC_RES_5_A_IVB)
> -
> -#define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(dev_priv, pipe,
> _PIPE_CRC_RES_RED_A)
> -#define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(dev_priv, pipe,
> _PIPE_CRC_RES_GREEN_A)
> -#define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(dev_priv, pipe,
> _PIPE_CRC_RES_BLUE_A)
> -#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(dev_priv, pipe,
> _PIPE_CRC_RES_RES1_A_I915)
> -#define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(dev_priv, pipe,
> _PIPE_CRC_RES_RES2_A_G4X)
> +#define PIPE_CRC_RES_1_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe,
> _PIPE_CRC_RES_1_A_IVB)
> +#define PIPE_CRC_RES_2_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe,
> _PIPE_CRC_RES_2_A_IVB)
> +#define PIPE_CRC_RES_3_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe,
> _PIPE_CRC_RES_3_A_IVB)
> +#define PIPE_CRC_RES_4_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe,
> _PIPE_CRC_RES_4_A_IVB)
> +#define PIPE_CRC_RES_5_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe,
> _PIPE_CRC_RES_5_A_IVB)
> +
> +#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv,
> pipe, _PIPE_CRC_RES_RED_A)
> +#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe,
> _PIPE_CRC_RES_GREEN_A)
> +#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv,
> pipe, _PIPE_CRC_RES_BLUE_A)
> +#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv,
> pipe, _PIPE_CRC_RES_RES1_A_I915)
> +#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv,
> pipe, _PIPE_CRC_RES_RES2_A_G4X)
>
> /* Pipe/transcoder A timing regs */
> #define _TRANS_HTOTAL_A 0x60000
> --
> 2.39.2
--
Ville Syrjälä
Intel
