On Thu, 09 May 2024, Arun R Murthy <[email protected]> wrote:
> uhbr13.5 is not supported on dg2/mtl. This patch removes the pll state
> table for synps and c20 PHY.
>
> Signed-off-by: Arun R Murthy <[email protected]>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 26 --------------
> drivers/gpu/drm/i915/display/intel_dp.c | 2 --
> drivers/gpu/drm/i915/display/intel_snps_phy.c | 35 -------------------
> 3 files changed, 63 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 8e3b13884bb8..fb07d14d9a7a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -885,31 +885,6 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr10
> = {
> },
> };
>
> -static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
> - .clock = 1350000, /* 13.5 Gbps */
> - .tx = { 0xbea0, /* tx cfg0 */
> - 0x4800, /* tx cfg1 */
> - 0x0000, /* tx cfg2 */
> - },
> - .cmn = {0x0500, /* cmn cfg0*/
> - 0x0005, /* cmn cfg1 */
> - 0x0000, /* cmn cfg2 */
> - 0x0000, /* cmn cfg3 */
> - },
> - .mpllb = { 0x015f, /* mpllb cfg0 */
> - 0x2205, /* mpllb cfg1 */
> - 0x1b17, /* mpllb cfg2 */
> - 0xffc1, /* mpllb cfg3 */
> - 0xe100, /* mpllb cfg4 */
> - 0xbd00, /* mpllb cfg5 */
> - 0x2000, /* mpllb cfg6 */
> - 0x0001, /* mpllb cfg7 */
> - 0x4800, /* mpllb cfg8 */
> - 0x0000, /* mpllb cfg9 */
> - 0x0000, /* mpllb cfg10 */
> - },
> -};
> -
> static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
> .clock = 2000000, /* 20 Gbps */
> .tx = { 0xbe20, /* tx cfg0 */
> @@ -940,7 +915,6 @@ static const struct intel_c20pll_state * const
> mtl_c20_dp_tables[] = {
> &mtl_c20_dp_hbr2,
> &mtl_c20_dp_hbr3,
> &mtl_c20_dp_uhbr10,
> - &mtl_c20_dp_uhbr13_5,
> &mtl_c20_dp_uhbr20,
> NULL,
> };
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7098ca65701f..a9c17c6d8d77 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -247,8 +247,6 @@ static void intel_dp_set_dpcd_sink_rates(struct intel_dp
> *intel_dp)
>
> if (uhbr_rates & DP_UHBR10)
> intel_dp->sink_rates[i++] = 1000000;
> - if (uhbr_rates & DP_UHBR13_5)
> - intel_dp->sink_rates[i++] = 1350000;
This is about the sink, not the source. We'll want to keep this.
BR,
Jani.
> if (uhbr_rates & DP_UHBR20)
> intel_dp->sink_rates[i++] = 2000000;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index e6df1f92def5..6b1eda0d73d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -213,47 +213,12 @@ static const struct intel_mpllb_state dg2_dp_uhbr10_100
> = {
> REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 76101),
> };
>
> -static const struct intel_mpllb_state dg2_dp_uhbr13_100 = {
> - .clock = 1350000,
> - .ref_control =
> - REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
> - .mpllb_cp =
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 45) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
> - .mpllb_div =
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3),
> - .mpllb_div2 =
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 508),
> - .mpllb_fracn1 =
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
> -
> - /*
> - * SSC will be enabled, DP UHBR has a minimum SSC requirement.
> - */
> - .mpllb_sscen =
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 79626),
> - .mpllb_sscstep =
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 102737),
> -};
> -
> static const struct intel_mpllb_state * const dg2_dp_100_tables[] = {
> &dg2_dp_rbr_100,
> &dg2_dp_hbr1_100,
> &dg2_dp_hbr2_100,
> &dg2_dp_hbr3_100,
> &dg2_dp_uhbr10_100,
> - &dg2_dp_uhbr13_100,
> NULL,
> };
--
Jani Nikula, Intel
