On Fri, 10 May 2024, Ville Syrjala <[email protected]> wrote:
> From: Ville Syrjälä <[email protected]>
>
> A few extra tabs have snuck into the skl+ plane register bit
> definitions. Remove them.
>
> Signed-off-by: Ville Syrjälä <[email protected]>

Reviewed-by: Jani Nikula <[email protected]>

> ---
>  drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h 
> b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> index 8ef9bd50d021..18dbe717ea21 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> @@ -199,17 +199,17 @@
>  
>  #define _PLANE_CUS_CTL_1_A                   0x701c8
>  #define   PLANE_CUS_ENABLE                   REG_BIT(31)
> -#define   PLANE_CUS_Y_PLANE_MASK                     REG_BIT(30)
> +#define   PLANE_CUS_Y_PLANE_MASK             REG_BIT(30)
>  #define   PLANE_CUS_Y_PLANE_4_RKL            
> REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
>  #define   PLANE_CUS_Y_PLANE_5_RKL            
> REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
>  #define   PLANE_CUS_Y_PLANE_6_ICL            
> REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
>  #define   PLANE_CUS_Y_PLANE_7_ICL            
> REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
> -#define   PLANE_CUS_HPHASE_SIGN_NEGATIVE             REG_BIT(19)
> +#define   PLANE_CUS_HPHASE_SIGN_NEGATIVE     REG_BIT(19)
>  #define   PLANE_CUS_HPHASE_MASK                      REG_GENMASK(17, 16)
>  #define   PLANE_CUS_HPHASE_0                 
> REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
>  #define   PLANE_CUS_HPHASE_0_25                      
> REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
>  #define   PLANE_CUS_HPHASE_0_5                       
> REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
> -#define   PLANE_CUS_VPHASE_SIGN_NEGATIVE             REG_BIT(15)
> +#define   PLANE_CUS_VPHASE_SIGN_NEGATIVE     REG_BIT(15)
>  #define   PLANE_CUS_VPHASE_MASK                      REG_GENMASK(13, 12)
>  #define   PLANE_CUS_VPHASE_0                 
> REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
>  #define   PLANE_CUS_VPHASE_0_25                      
> REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)

-- 
Jani Nikula, Intel

Reply via email to