> -----Original Message-----
> From: Intel-xe <[email protected]> On Behalf Of Suraj
> Kandpal
> Sent: Monday, July 22, 2024 12:15 PM
> To: [email protected]; [email protected]
> Cc: Nautiyal, Ankit K <[email protected]>; Kandpal, Suraj
> <[email protected]>
> Subject: [PATCH 3/3] drm/xe/hdcp: Check GSC structure validity
>
> Sometimes xe_gsc is not initialized when checked at HDCP capability check.
> Add gsc structure check to avoid null pointer error.
>
> Signed-off-by: Suraj Kandpal <[email protected]>
LGTM. Thanks.
Reviewed-by: Dnyaneshwar Bhadane <[email protected]>
> ---
> drivers/gpu/drm/xe/display/xe_hdcp_gsc.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
> b/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
> index 990285aa9b26..0af667ebebf9 100644
> --- a/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
> +++ b/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
> @@ -40,10 +40,14 @@ bool intel_hdcp_gsc_check_status(struct xe_device
> *xe) {
> struct xe_tile *tile = xe_device_get_root_tile(xe);
> struct xe_gt *gt = tile->media_gt;
> + struct xe_gsc *gsc = >->uc.gsc;
> bool ret = true;
>
> - if (!xe_uc_fw_is_enabled(>->uc.gsc.fw))
> + if (!gsc && !xe_uc_fw_is_enabled(&gsc->fw)) {
> + drm_dbg_kms(&xe->drm,
> + "GSC Components not ready for HDCP2.x\n");
> return false;
> + }
>
> xe_pm_runtime_get(xe);
> if (xe_force_wake_get(gt_to_fw(gt), XE_FW_GSC)) { @@ -53,7 +57,7
> @@ bool intel_hdcp_gsc_check_status(struct xe_device *xe)
> goto out;
> }
>
> - if (!xe_gsc_proxy_init_done(>->uc.gsc))
> + if (!xe_gsc_proxy_init_done(gsc))
> ret = false;
>
> xe_force_wake_put(gt_to_fw(gt), XE_FW_GSC);
> --
> 2.43.2
