To support upcoming patches, we need to store the current mask for active CCS engines.
Active engines refer to those exposed to userspace via the UABI engine list. Signed-off-by: Andi Shyti <[email protected]> --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 20 ++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 + 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 49493928f714..01ce719cf475 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -9,6 +9,23 @@ #include "intel_gt_regs.h" #include "intel_gt_sysfs.h" +static void update_ccs_mask(struct intel_gt *gt, u32 ccs_mode) +{ + unsigned long cslices_mask = CCS_MASK(gt); + int i; + + /* Mask off all the CCS engines */ + gt->ccs.ccs_mask = 0; + + for_each_set_bit(i, &cslices_mask, I915_MAX_CCS) { + gt->ccs.ccs_mask |= BIT(i); + + ccs_mode--; + if (!ccs_mode) + break; + } +} + void intel_gt_apply_ccs_mode(struct intel_gt *gt, u32 mode) { unsigned long cslices_mask = CCS_MASK(gt); @@ -91,6 +108,9 @@ void intel_gt_apply_ccs_mode(struct intel_gt *gt, u32 mode) void intel_gt_ccs_mode_init(struct intel_gt *gt) { mutex_init(>->ccs.mutex); + + /* Set CCS balance mode 1 in the ccs_mask */ + update_ccs_mask(gt, 1); } static ssize_t num_cslices_show(struct device *dev, diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index a833b395237b..235b4b81eecd 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -220,6 +220,7 @@ struct intel_gt { struct { struct mutex mutex; u32 mode_reg_val; + intel_engine_mask_t ccs_mask; } ccs; /* -- 2.45.2
