On Mon, 09 Sep 2024, Ville Syrjälä <[email protected]> wrote:
> On Mon, Sep 09, 2024 at 03:15:37PM +0300, Jani Nikula wrote:
>> While the struct intel_pps vlv_pps_pipe and vlv_active_pipe members are
>> only relevant for VLV/CHV, we still initialize them on all platforms and
>> check them on BXT/GLK. Wrap all access inside VLV/CHV checks for
>> consistency.
>>
>> Signed-off-by: Jani Nikula <[email protected]>
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
>> drivers/gpu/drm/i915/display/intel_pps.c | 11 ++++++-----
>> 2 files changed, 9 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index bc1ec9440a4d..7e36a7820fec 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -6843,8 +6843,6 @@ intel_dp_init_connector(struct intel_digital_port
>> *dig_port,
>> return false;
>>
>> intel_dp->reset_link_params = true;
>> - intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
>> - intel_dp->pps.vlv_active_pipe = INVALID_PIPE;
>>
>> /* Preserve the current hw state. */
>> intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
>> @@ -6871,8 +6869,10 @@ intel_dp_init_connector(struct intel_digital_port
>> *dig_port,
>> intel_dp_set_default_sink_rates(intel_dp);
>> intel_dp_set_default_max_sink_lane_count(intel_dp);
>>
>> - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>> + intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
>> intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp);
>> + }
>>
>> intel_dp_aux_init(intel_dp);
>> intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
>> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
>> b/drivers/gpu/drm/i915/display/intel_pps.c
>> index b7c73842ea16..2fb32ac1b7cf 100644
>> --- a/drivers/gpu/drm/i915/display/intel_pps.c
>> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
>> @@ -472,16 +472,17 @@ void intel_pps_reset_all(struct intel_display *display)
>> for_each_intel_dp(display->drm, encoder) {
>> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>
>> - drm_WARN_ON(display->drm,
>> - intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
>> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>> + drm_WARN_ON(display->drm,
>> + intel_dp->pps.vlv_active_pipe !=
>> INVALID_PIPE);
>>
>> if (encoder->type != INTEL_OUTPUT_EDP)
>> continue;
>>
>> - if (DISPLAY_VER(display) >= 9)
>> - intel_dp->pps.pps_reset = true;
>> - else
>> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>> intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
>> + else
>> + intel_dp->pps.pps_reset = true;
>
> You are now setting that for all pre-skl except vlv/chv.
Above context in intel_pps_reset_all():
if (drm_WARN_ON(display->drm, !IS_LP(dev_priv)))
i.e. VLV/CHV/BXT/GLK only.
BR,
Jani.
>
>> }
>> }
>>
>> --
>> 2.39.2
--
Jani Nikula, Intel
