On Tue, 10 Sep 2024, Ville Syrjala <[email protected]> wrote: > From: Ville Syrjälä <[email protected]> > > The SPI code rounds the VBT allocation to a multiple of four bytes > (presumably because it reads the VBT 4 bytes at a time). Do the > same for the PCI ROM side to eliminate pointless differences between > the two codepaths. This will make no functional difference. > > Signed-off-by: Ville Syrjälä <[email protected]>
Reviewed-by: Jani Nikula <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_bios.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c > b/drivers/gpu/drm/i915/display/intel_bios.c > index 86b81fd23f58..cc4a4cc2bf3e 100644 > --- a/drivers/gpu/drm/i915/display/intel_bios.c > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > @@ -3166,7 +3166,7 @@ static struct vbt_header *oprom_get_vbt(struct > intel_display *display, > } > > /* The rest will be validated by intel_bios_is_valid_vbt() */ > - vbt = kmalloc(vbt_size, GFP_KERNEL); > + vbt = kmalloc(round_up(vbt_size, 4), GFP_KERNEL); > if (!vbt) > goto err_unmap_oprom; -- Jani Nikula, Intel
