Figure 3-52: 128b132b DP DPTC LANEx_CHANNEL_EQ_DONE Sequence of DP2.1a spec. During LT, the transmitter shall read DPCD 02216h before DPCD 00202h through 00207h, and 0200Ch through 0200Fh
Co-developed-by: Srikanth V NagaVenkata <[email protected]> Signed-off-by: Arun R Murthy <[email protected]> --- .../gpu/drm/i915/display/intel_dp_link_training.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index f41b69840ad9..460426a3b506 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1419,12 +1419,6 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp, for (try = 0; try < max_tries; try++) { fsleep(delay_us); - /* - * The delay may get updated. The transmitter shall read the - * delay before link status during link training. - */ - delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); - if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); return false; @@ -1451,6 +1445,12 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp, if (time_after(jiffies, deadline)) timeout = true; /* try one last time after deadline */ + /* + * During LT, Tx shall read DPCD 02216h before DPCD 00202h to 00207h and + * 0200Ch through 0200Fh. + */ + delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); + /* Update signal levels and training set as requested. */ intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status); if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { -- 2.25.1
