On Thu, Oct 03, 2024 at 05:44:12PM +0200, Maarten Lankhorst wrote: > I'm planning to reorder readout in the Xe sequence in such a way that > interrupts will not be available, so just use an async flip. > > Since the new FB points to the same pages, it will not tear. It also > has the benefit of perhaps being slightly faster. > > Signed-off-by: Maarten Lankhorst <[email protected]> > --- > drivers/gpu/drm/i915/display/skl_universal_plane.c | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c > b/drivers/gpu/drm/i915/display/skl_universal_plane.c > index fdb141cfa4274..73a3624e34098 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > @@ -2800,7 +2800,7 @@ bool skl_fixup_initial_plane_config(struct intel_crtc > *crtc, > to_intel_plane_state(plane->base.state); > enum plane_id plane_id = plane->id; > enum pipe pipe = crtc->pipe; > - u32 base; > + u32 base, plane_ctl; > > if (!plane_state->uapi.visible) > return false; > @@ -2814,7 +2814,16 @@ bool skl_fixup_initial_plane_config(struct intel_crtc > *crtc, > if (plane_config->base == base) > return false; > > + /* Perform an async flip to the new surface. */ > + plane_ctl = intel_read(i915, PLANE_CTL(pipe, plane_id)); > + plane_ctl |= PLANE_CTL_ASYNC_FLIP; > +
No async flips! > + intel_de_write(i915, PLANE_CTL(pipe, plane_id), plane_ctl); > intel_de_write(i915, PLANE_SURF(pipe, plane_id), base); > > - return true; > + if (intel_de_wait_custom(i915, PLANE_SURFLIVE(pipe, plane_id), ~0U, > base, 0, 40, NULL) < 0) > + drm_warn(&i915->drm, "async flip timed out\n"); > + > + /* No need to vblank wait either */ > + return false; > } > -- > 2.45.2 -- Ville Syrjälä Intel
