On Tue, 08 Oct 2024, Matt Atwood <[email protected]> wrote: > From: Suraj Kandpal <[email protected]> > > Add condition for P2.PG power down value. > > Bspec: 74494 > Signed-off-by: Suraj Kandpal <[email protected]> > Signed-off-by: Matt Atwood <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index 1c8c2a2b05e1..3d95ee65a9f1 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -3144,7 +3144,8 @@ static u8 cx0_power_control_disable_val(struct > intel_encoder *encoder) > if (intel_encoder_is_c10phy(encoder)) > return CX0_P2PG_STATE_DISABLE; > > - if (IS_BATTLEMAGE(i915) && encoder->port == PORT_A) > + if ((IS_BATTLEMAGE(i915) && encoder->port == PORT_A) || > + (DISPLAY_VER(i915) >= 30 && encoder->type == INTEL_OUTPUT_EDP)) > return CX0_P2PG_STATE_DISABLE;
Does this match what the subject says? BR, Jani. > > return CX0_P4PG_STATE_DISABLE; -- Jani Nikula, Intel
