On Mon, 11 Nov 2024, Ankit Nautiyal <[email protected]> wrote:
> VRR timing generator can be used in multiple modes: dynamic vrr, fixed
> refresh rate and content matched refresh rate (cmrr).
> Currently we support dynamic vrr mode and cmrr mode, so add a new member
> to track in which mode the VRR timing generator is used.
>
> Signed-off-by: Ankit Nautiyal <[email protected]>
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d3a1aa7c919f..a1b67e76d91c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -913,6 +913,12 @@ void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg,
> u32 val);
>
> typedef void (*intel_io_reg_write)(void *ctx, i915_reg_t reg, u32 val);
>
> +enum intel_vrrtg_mode {
> + INTEL_VRRTG_MODE_NONE,
I couldn't quickly conclude whether this is in fact redundant with
tg_enable.
Would it be possible to ditch this in favor of using mode != NONE?
BR,
Jani.
> + INTEL_VRRTG_MODE_VRR,
> + INTEL_VRRTG_MODE_CMRR,
> +};
> +
> struct intel_crtc_state {
> /*
> * uapi (drm) state. This is the software state shown to userspace.
> @@ -1286,6 +1292,7 @@ struct intel_crtc_state {
> u8 pipeline_full;
> u16 flipline, vmin, vmax, guardband;
> u32 vsync_end, vsync_start;
> + enum intel_vrrtg_mode mode;
> } vrr;
>
> /* Content Match Refresh Rate state */
--
Jani Nikula, Intel
