On Thu, 16 Jan 2025, Ville Syrjala <[email protected]> wrote: > From: Ville Syrjälä <[email protected]> > > I want to start using intel_set_transcoder_timings_lrr() also for > fixing up the vblank delay during boot. To that end make sure it > can cope with interlaced modes as well. > > Note that we have soft-defeatured interlaced modes on tgl+ so > technically this is dead code, but if we ever have the need to > bring interlaced support back it seems better to handle this.
I might've added that as a comment in code, but *shrug*. Reviewed-by: Jani Nikula <[email protected]> > > Cc: Paz Zcharya <[email protected]> > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 5ba3b2d658e5..1260e394afc7 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -2923,6 +2923,12 @@ static void intel_set_transcoder_timings_lrr(const > struct intel_crtc_state *crtc > crtc_vblank_start = adjusted_mode->crtc_vblank_start; > crtc_vblank_end = adjusted_mode->crtc_vblank_end; > > + if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { > + /* the chip adds 2 halflines automatically */ > + crtc_vtotal -= 1; > + crtc_vblank_end -= 1; > + } > + > if (DISPLAY_VER(dev_priv) >= 13) { > /* > * VBLANK_START not used by hw, just clear it > @@ -2931,8 +2937,6 @@ static void intel_set_transcoder_timings_lrr(const > struct intel_crtc_state *crtc > crtc_vblank_start = 1; > } > > - drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & > DRM_MODE_FLAG_INTERLACE); > - > /* > * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode. > * But let's write it anyway to keep the state checker happy. -- Jani Nikula, Intel
