On Mon, 2025-02-03 at 17:58 -0300, Gustavo Sousa wrote: > The Bspec has been updated to include INITIATE_PM_DMD_REQ in the set of > register offsets that require the DMC wakelock for access during DC5. > Update our table accordingly. > > Bspec: 71583 > Signed-off-by: Gustavo Sousa <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_dmc_wl.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c > b/drivers/gpu/drm/i915/display/intel_dmc_wl.c > index 43884740f8ea..86ba159b683c 100644 > --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c > +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c > @@ -102,6 +102,7 @@ static const struct intel_dmc_wl_range > xe3lpd_dc5_dc6_dmc_ranges[] = { > { .start = 0x42088 }, /* CHICKEN_MISC_3 */ > { .start = 0x46160 }, /* CMTG_CLK_SEL */ > { .start = 0x8f000, .end = 0x8ffff }, /* Main DMC registers */ > + { .start = 0x45230 }, /* INITIATE_PM_DMD_REQ */ > > {}, > };
Matches the bspec. Reviewed-by: Luca Coelho <[email protected]> -- Cheers, Luca.
