On Thu, 06 Mar 2025, Ville Syrjala <ville.syrj...@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> According to the DP spec TPS4 is mandatory for HBR3. We have
> however seen some broken eDP sinks that violate this and
> declare support for HBR3 without TPS4 support.
>
> At least in the case of the icl Dell XPS 13 7390 this results
> in an unstable output.
>
> Reject HBR3 when TPS4 supports is unavailable on the sink.
>
> v2: Leave breadcrumbs in dmesg to avoid head scratching (Jani)
>
> Cc: sta...@vger.kernel.org
> Cc: Jani Nikula <jani.nik...@linux.intel.com>
> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5969
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nik...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 49 +++++++++++++++++++++----
> 1 file changed, 42 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 205ec315b413..70f5d1465f81 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -172,10 +172,28 @@ int intel_dp_link_symbol_clock(int rate)
>
> static int max_dprx_rate(struct intel_dp *intel_dp)
> {
> + struct intel_display *display = to_intel_display(intel_dp);
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> + int max_rate;
> +
> if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
> - return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);
> + max_rate = drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);
> + else
> + max_rate =
> drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
>
> - return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
> + /*
> + * Some broken eDP sinks illegally declare support for
> + * HBR3 without TPS4, and are unable to produce a stable
> + * output. Reject HBR3 when TPS4 is not available.
> + */
> + if (max_rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) {
> + drm_dbg_kms(display->drm,
> + "[ENCODER:%d:%s] Rejecting HBR3 due to missing TPS4
> support\n",
> + encoder->base.base.id, encoder->base.name);
> + max_rate = 540000;
> + }
> +
> + return max_rate;
> }
>
> static int max_dprx_lane_count(struct intel_dp *intel_dp)
> @@ -4170,6 +4188,9 @@ static void intel_edp_mso_init(struct intel_dp
> *intel_dp)
> static void
> intel_edp_set_sink_rates(struct intel_dp *intel_dp)
> {
> + struct intel_display *display = to_intel_display(intel_dp);
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> +
> intel_dp->num_sink_rates = 0;
>
> if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
> @@ -4180,10 +4201,7 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
> sink_rates, sizeof(sink_rates));
>
> for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
> - int val = le16_to_cpu(sink_rates[i]);
> -
> - if (val == 0)
> - break;
> + int rate;
>
> /* Value read multiplied by 200kHz gives the per-lane
> * link rate in kHz. The source rates are, however,
> @@ -4191,7 +4209,24 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
> * back to symbols is
> * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
> */
> - intel_dp->sink_rates[i] = (val * 200) / 10;
> + rate = le16_to_cpu(sink_rates[i]) * 200 / 10;
> +
> + if (rate == 0)
> + break;
> +
> + /*
> + * Some broken eDP sinks illegally declare support for
> + * HBR3 without TPS4, and are unable to produce a stable
> + * output. Reject HBR3 when TPS4 is not available.
> + */
> + if (rate >= 810000 &&
> !drm_dp_tps4_supported(intel_dp->dpcd)) {
> + drm_dbg_kms(display->drm,
> + "[ENCODER:%d:%s] Rejecting HBR3 due
> to missing TPS4 support\n",
> + encoder->base.base.id,
> encoder->base.name);
> + break;
> + }
> +
> + intel_dp->sink_rates[i] = rate;
> }
> intel_dp->num_sink_rates = i;
> }
--
Jani Nikula, Intel
