Add register to access DC Balance registers. Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_vrr_regs.h | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h index 6ed0e0dc97e7..6297108f1357 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h @@ -9,6 +9,20 @@ #include "intel_display_reg_defs.h" /* VRR registers */ +#define _TRANS_VRR_VMAX_DCB_A 0x60414 /* lnl+ */ +#define _TRANS_VRR_VMAX_DCB_B 0x61414 /* lnl+ */ +#define TRANS_VRR_VMAX_DCB(trans) _MMIO_TRANS((trans), \ + _TRANS_VRR_VMAX_DCB_A, \ + _TRANS_VRR_VMAX_DCB_B) +#define VRR_VMAX_DCB_MASK REG_GENMASK(19, 0) + +#define _TRANS_VRR_FLIPLINE_DCB_A 0x60418 /* lnl+ */ +#define _TRANS_VRR_FLIPLINE_DCB_B 0x61418 /* lnl+ */ +#define TRANS_VRR_FLIPLINE_DCB(trans) _MMIO_TRANS((trans), \ + _TRANS_VRR_FLIPLINE_DCB_A, \ + _TRANS_VRR_FLIPLINE_DCB_B) +#define VRR_FLIPLINE_DCB_MASK REG_GENMASK(19, 0) + #define _TRANS_VRR_CTL_A 0x60420 #define _TRANS_VRR_CTL_B 0x61420 #define _TRANS_VRR_CTL_C 0x62420 @@ -17,6 +31,7 @@ #define VRR_CTL_VRR_ENABLE REG_BIT(31) #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) +#define VRR_CTL_DCB_ADJ_ENABLE REG_BIT(28) /* lnl+ */ #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) @@ -93,6 +108,34 @@ #define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A) #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A 0x604c0 /* lnl+ */ +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B 0x614c0 /* lnl+ */ +#define TRANS_ADAPTIVE_SYNC_DCB_CTL(trans) _MMIO_TRANS((trans), \ + _TRANS_ADAPTIVE_SYNC_DCB_CTL_A, \ + _TRANS_ADAPTIVE_SYNC_DCB_CTL_B) +#define ADAPTIVE_SYNC_COUNTER_EN REG_BIT(31) +#define ADAPTIVE_SYNC_COUNTER_RESET REG_BIT(30) +#define ADAPTIVE_SYNC_ODD_COUNTER_OVERFLOW REG_BIT(15) +#define ADAPTIVE_SYNC_EVEN_COUNTER_OVERFLOW REG_BIT(14) +#define ADAPTIVE_SYNC_ODD_LINE_COUNTER_OVERFLOW REG_BIT(13) +#define ADAPTIVE_SYNC_EVEN_LINE_COUNTER_OVERFLOW REG_BIT(12) + +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A 0x604d4 /* lnl+ */ +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B 0x614d4 /* lnl+ */ +#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(trans) _MMIO_TRANS((trans), \ + _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A, \ + _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B) +#define VRR_DCB_ADJ_FLIPLINE_CNT_MASK REG_GENMASK(31, 24) +#define VRR_DCB_ADJ_FLIPLINE_MASK REG_GENMASK(19, 0) + +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A 0x604d8 /* lnl+ */ +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B 0x614d8 /* lnl+ */ +#define TRANS_VRR_DCB_ADJ_VMAX_CFG(trans) _MMIO_TRANS((trans), \ + _TRANS_VRR_DCB_ADJ_VMAX_CFG_A, \ + _TRANS_VRR_DCB_ADJ_VMAX_CFG_B) +#define VRR_DCB_ADJ_VMAX_CNT_MASK REG_GENMASK(31, 24) +#define VRR_DCB_ADJ_VMAX_MASK REG_GENMASK(19, 0) + #define _TRANS_PUSH_A 0x60a70 #define _TRANS_PUSH_B 0x61a70 #define _TRANS_PUSH_C 0x62a70 -- 2.48.1
