Re: [PATCH v2 05/13] drm/i915/vrr: Add compute config for DC balance params

[Nautiyal, Ankit K]

On 4/21/2025 9:18 PM, Mitul Golani wrote:
Add compute config for DC balance params. This will be required
to calculate correct balance requirement for DMC firmware.
Subject can simply be Compute DC balance parameters.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com>
---
  drivers/gpu/drm/i915/display/intel_vrr.c | 21 +++++++++++++++++++++
  1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
b/drivers/gpu/drm/i915/display/intel_vrr.c
index c4fb78d86ab0..383024dc2784 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -16,6 +16,9 @@
  
  #define FIXED_POINT_PRECISION		100
  #define CMRR_PRECISION_TOLERANCE      10
+#define DCB_CORRECTION_SENSITIVITY     30
+#define DCB_CORRECTION_AGGRESSIVENESS  1000
+#define DCB_BLANK_TARGET               50

It would be good to document that whether these values are based on some 
experimentation or some golden values.


  
  bool intel_vrr_is_capable(struct intel_connector *connector)
  {
@@ -409,6 +412,24 @@ intel_vrr_compute_config(struct intel_crtc_state 
*crtc_state,
                        (crtc_state->hw.adjusted_mode.crtc_vtotal -
                         crtc_state->hw.adjusted_mode.vsync_end);
        }
+
+       if (crtc_state->vrr.dc_balance.enable && HAS_DC_BALANCE(display)) {

Perhaps check for HAS_DC_BALANCE() first.

Regards,

Ankit

+               crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax;
+               crtc_state->vrr.dc_balance.vmin = crtc_state->vrr.vmin;
+               crtc_state->vrr.dc_balance.max_increase =
+                       crtc_state->vrr.vmax - crtc_state->vrr.vmin;
+               crtc_state->vrr.dc_balance.max_decrease =
+                       crtc_state->vrr.vmax - crtc_state->vrr.vmin;
+               crtc_state->vrr.dc_balance.guardband =
+               DIV_ROUND_UP(crtc_state->vrr.dc_balance.vmax * 
DCB_CORRECTION_SENSITIVITY,
+                            100);
+               crtc_state->vrr.dc_balance.slope =
+                       DIV_ROUND_UP(DCB_CORRECTION_AGGRESSIVENESS * 10,
+                                    crtc_state->vrr.dc_balance.guardband);
+               crtc_state->vrr.dc_balance.vblank_target =
+               DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) * 
DCB_BLANK_TARGET,
+                            100);
+       }
  }
  
  void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)