For newer platforms (post DG2) hardware intentionally stalls on submisstion of concurrent RCS and CCS of different address spaces. With this workaround GuC will never schedule such conlicting contexts; preventing detection of a stall as a hang.
GuC specs recommend to enable this for all platforms starting from MTL supporting CCS. v2: Use existing macros for version check. (Jani) Signed-off-by: Julia Filipchuk <[email protected]> --- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index 9df80c325fc1..a4019d3e71a8 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -313,8 +313,12 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) * * The same WA bit is used for both and 22011391025 is applicable to * all DG2. + * + * Platforms post DG2 prevent behavior in hardware. This is implicitly + * enabled to give guc management over CCS scheduling. */ - if (IS_DG2(gt->i915)) + if (IS_DG2(gt->i915) || + (CCS_MASK(gt) && GRAPHICS_VER_FULL((gt)->i915) >= IP_VER(12, 70))) flags |= GUC_WA_DUAL_QUEUE; /* Wa_22011802037: graphics version 11/12 */ @@ -322,8 +326,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) flags |= GUC_WA_PRE_PARSER; /* - * Wa_22012727170 - * Wa_22012727685 + * Wa_22012727170 Wa_22012727685 */ if (IS_DG2_G11(gt->i915)) flags |= GUC_WA_CONTEXT_ISOLATION; -- 2.49.0
