On Mon, 2025-04-28 at 16:31 +0300, Imre Deak wrote:
> A follow up change will check a selected bpp's BW requirement in
> intel_dp_mtp_tu_compute_config(), however that requires the total link
> slot count to be up-to-date. The latter in turn depends on the channel
> encoding and hence the link rate used, so it can be set after the
> link rate used is selected.
>
> This also allows simplifying mst_stream_update_slots(), do that as well,
> moving the function definition before its use.
>
> Cc: Jani Nikula <jani.nik...@intel.com>
> Signed-off-by: Imre Deak <imre.d...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 36 +++++++--------------
> 1 file changed, 11 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 8e1ed3b38217d..59afb550cd0cc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -261,6 +261,15 @@ static void intel_dp_mst_compute_min_hblank(struct
> intel_crtc_state *crtc_state,
> crtc_state->min_hblank = hblank;
> }
>
> +static void mst_stream_update_slots(const struct intel_crtc_state
> *crtc_state,
> + struct drm_dp_mst_topology_state
> *topology_state)
> +{
> + u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?
> + DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B;
> +
> + drm_dp_mst_update_slots(topology_state, link_coding_cap);
> +}
> +
> int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state,
> struct drm_connector_state *conn_state,
> @@ -296,6 +305,8 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp
> *intel_dp,
>
> mst_state->pbn_div =
> drm_dp_get_vc_payload_bw(crtc_state->port_clock,
>
> crtc_state->lane_count);
> +
> + mst_stream_update_slots(crtc_state, mst_state);
> }
>
> if (dsc) {
> @@ -513,27 +524,6 @@ static int mst_stream_dsc_compute_link_config(struct
> intel_dp *intel_dp,
> fxp_q4_from_int(1), true);
> }
>
> -static int mst_stream_update_slots(struct intel_dp *intel_dp,
> - struct intel_crtc_state *crtc_state,
> - struct drm_connector_state *conn_state)
> -{
> - struct intel_display *display = to_intel_display(intel_dp);
> - struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst.mgr;
> - struct drm_dp_mst_topology_state *topology_state;
> - u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?
> - DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B;
> -
> - topology_state = drm_atomic_get_mst_topology_state(conn_state->state,
> mgr);
> - if (IS_ERR(topology_state)) {
> - drm_dbg_kms(display->drm, "slot update failed\n");
> - return PTR_ERR(topology_state);
> - }
> -
> - drm_dp_mst_update_slots(topology_state, link_coding_cap);
> -
> - return 0;
> -}
> -
> static int mode_hblank_period_ns(const struct drm_display_mode *mode)
> {
> return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(mode->htotal - mode->hdisplay,
> @@ -736,10 +726,6 @@ static int mst_stream_compute_config(struct
> intel_encoder *encoder,
> pipe_config->dp_m_n.tu);
> }
>
> - if (ret)
> - return ret;
> -
> - ret = mst_stream_update_slots(intel_dp, pipe_config, conn_state);
> if (ret)
> return ret;
>
Reviewed-by: Luca Coelho <luciano.coe...@intel.com>
--
Cheers,
Luca.
