On 5/6/2025 8:25 PM, Mitul Golani wrote:
From: Ville Syrjälä <ville.syrj...@linux.intel.com>
Add pipe dmc registers and access bits for DC Balance params
configuration and enablement.
--v2:
- Separate register definitions for transcoder and
pipe dmc. (Ankit)
- Use MMIO pipe macros instead of transcoder ones. (Ankit)
- Remove dev_priv use. (Jani, Nikula)
Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 46 +++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index e16ea3f16ed8..7c4bffce4cf5 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -117,4 +117,50 @@
#define DMC_WAKELOCK_CTL_REQ REG_BIT(31)
#define DMC_WAKELOCK_CTL_ACK REG_BIT(15)
+#define _PIPEDMC_DCB_CTL_A 0x5F1A0
+#define _PIPEDMC_DCB_CTL_B 0x5F5A0
As per i915_reg.h documentation: Use lower case in hexadecimal values
Though it seems we are not following this very closely, but lets follow
documentation for the new registers.
With above fixed:
Reviewed-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
+#define PIPEDMC_DCB_CTL(pipe) _MMIO_PIPE((pipe),
_PIPEDMC_DCB_CTL_A,\
+ _PIPEDMC_DCB_CTL_B)
+#define PIPEDMC_ADAPTIVE_DCB_ENABLE REG_BIT(31)
+
+#define _PIPEDMC_DCB_VBLANK_A 0x5F1BC
+#define _PIPEDMC_DCB_VBLANK_B 0x5F5BC
+#define PIPEDMC_DCB_VBLANK(pipe) _MMIO_PIPE((pipe),
_PIPEDMC_DCB_VBLANK_A,\
+
_PIPEDMC_DCB_VBLANK_B)
+
+#define _PIPEDMC_DCB_SLOPE_A 0x5F1B8
+#define _PIPEDMC_DCB_SLOPE_B 0x5F5B8
+#define PIPEDMC_DCB_SLOPE(pipe) _MMIO_PIPE((pipe),
_PIPEDMC_DCB_SLOPE_A,\
+ _PIPEDMC_DCB_SLOPE_B)
+
+#define _PIPEDMC_DCB_GUARDBAND_A 0x5F1B4
+#define _PIPEDMC_DCB_GUARDBAND_B 0x5F5B4
+#define PIPEDMC_DCB_GUARDBAND(pipe) _MMIO_PIPE((pipe),
_PIPEDMC_DCB_GUARDBAND_A,\
+
_PIPEDMC_DCB_GUARDBAND_B)
+
+#define _PIPEDMC_DCB_MAX_INCREASE_A 0x5F1AC
+#define _PIPEDMC_DCB_MAX_INCREASE_B 0x5F5AC
+#define PIPEDMC_DCB_MAX_INCREASE(pipe) _MMIO_PIPE((pipe),
_PIPEDMC_DCB_MAX_INCREASE_A,\
+
_PIPEDMC_DCB_MAX_INCREASE_B)
+
+#define _PIPEDMC_DCB_MAX_DECREASE_A 0x5F1B0
+#define _PIPEDMC_DCB_MAX_DECREASE_B 0x5F5B0
+#define PIPEDMC_DCB_MAX_DECREASE(pipe) _MMIO_PIPE((pipe),
_PIPEDMC_DCB_MAX_DECREASE_A,\
+
_PIPEDMC_DCB_MAX_DECREASE_B)
+
+#define _PIPEDMC_DCB_VMIN_A 0x5F1A4
+#define _PIPEDMC_DCB_VMIN_B 0x5F5A4
+#define PIPEDMC_DCB_VMIN(pipe) _MMIO_PIPE((pipe),
_PIPEDMC_DCB_VMIN_A,\
+ _PIPEDMC_DCB_VMIN_B)
+
+#define _PIPEDMC_DCB_VMAX_A 0x5F1A8
+#define _PIPEDMC_DCB_VMAX_B 0x5F5A8
+#define PIPEDMC_DCB_VMAX(pipe) _MMIO_PIPE((pipe),
_PIPEDMC_DCB_VMAX_A,\
+ _PIPEDMC_DCB_VMAX_B)
+
+#define _PIPEDMC_DCB_DEBUG_A 0x5f1c0
+#define _PIPEDMC_DCB_DEBUG_B 0x5f5c0
+#define PIPEDMC_DCB_DEBUG(pipe) _MMIO_PIPE(pipe,
_PIPEDMC_DCB_DEBUG_A,\
+ _PIPEDMC_DCB_DEBUG_B)
+
#endif /* __INTEL_DMC_REGS_H__ */
