On Fri, 09 May 2025, Suraj Kandpal <suraj.kand...@intel.com> wrote:
> Rename crtc_get_shared_dpll to take into the individual PLL framework
> which came in at DISPLAY_VER >= 14.
>
> --v2
> -Change naming to dpll_global to keep consistency with rest of the
> naming
>
> --v3
> -Just use intel_dpll [Jani]
>
> Signed-off-by: Suraj Kandpal <suraj.kand...@intel.com>
Having shared dpll stuff also in intel_dpll.c is just confusing...
Reviewed-by: Jani Nikula <jani.nik...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dpll.c | 24 ++++++++++----------
> drivers/gpu/drm/i915/display/intel_dpll.h | 4 ++--
> 3 files changed, 15 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index ce5c9e74475d..b091faff6680 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4225,7 +4225,7 @@ static int intel_crtc_atomic_check(struct
> intel_atomic_state *state,
> crtc_state->update_wm_post = true;
>
> if (intel_crtc_needs_modeset(crtc_state)) {
> - ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
> + ret = intel_dpll_crtc_get_dpll(state, crtc);
> if (ret)
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index db67e92505d2..e25411c4171c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -27,8 +27,8 @@
> struct intel_dpll_global_funcs {
> int (*crtc_compute_clock)(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> - int (*crtc_get_shared_dpll)(struct intel_atomic_state *state,
> - struct intel_crtc *crtc);
> + int (*crtc_get_dpll)(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> };
>
> struct intel_limit {
> @@ -1176,8 +1176,8 @@ static int hsw_crtc_compute_clock(struct
> intel_atomic_state *state,
> return 0;
> }
>
> -static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> +static int hsw_crtc_get_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> struct intel_display *display = to_intel_display(state);
> struct intel_crtc_state *crtc_state =
> @@ -1404,8 +1404,8 @@ static int ilk_crtc_compute_clock(struct
> intel_atomic_state *state,
> return ret;
> }
>
> -static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> +static int ilk_crtc_get_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> @@ -1700,12 +1700,12 @@ static const struct intel_dpll_global_funcs
> dg2_dpll_funcs = {
>
> static const struct intel_dpll_global_funcs hsw_dpll_funcs = {
> .crtc_compute_clock = hsw_crtc_compute_clock,
> - .crtc_get_shared_dpll = hsw_crtc_get_shared_dpll,
> + .crtc_get_dpll = hsw_crtc_get_dpll,
> };
>
> static const struct intel_dpll_global_funcs ilk_dpll_funcs = {
> .crtc_compute_clock = ilk_crtc_compute_clock,
> - .crtc_get_shared_dpll = ilk_crtc_get_shared_dpll,
> + .crtc_get_dpll = ilk_crtc_get_dpll,
> };
>
> static const struct intel_dpll_global_funcs chv_dpll_funcs = {
> @@ -1758,8 +1758,8 @@ int intel_dpll_crtc_compute_clock(struct
> intel_atomic_state *state,
> return 0;
> }
>
> -int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> +int intel_dpll_crtc_get_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> struct intel_display *display = to_intel_display(state);
> struct intel_crtc_state *crtc_state =
> @@ -1772,10 +1772,10 @@ int intel_dpll_crtc_get_shared_dpll(struct
> intel_atomic_state *state,
> if (!crtc_state->hw.enable || crtc_state->intel_dpll)
> return 0;
>
> - if (!display->funcs.dpll->crtc_get_shared_dpll)
> + if (!display->funcs.dpll->crtc_get_dpll)
> return 0;
>
> - ret = display->funcs.dpll->crtc_get_shared_dpll(state, crtc);
> + ret = display->funcs.dpll->crtc_get_dpll(state, crtc);
> if (ret) {
> drm_dbg_kms(display->drm, "[CRTC:%d:%s] Couldn't get a shared
> DPLL\n",
> crtc->base.base.id, crtc->base.name);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h
> b/drivers/gpu/drm/i915/display/intel_dpll.h
> index 280e90a57c87..3444a2dd3166 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.h
> @@ -19,8 +19,8 @@ struct intel_dpll_hw_state;
> void intel_dpll_init_clock_hook(struct intel_display *display);
> int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> -int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
> - struct intel_crtc *crtc);
> +int intel_dpll_crtc_get_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
> u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
> void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
--
Jani Nikula, Intel
