On Thu, Mar 27, 2014 at 06:00:08PM +0000, oscar.ma...@intel.com wrote:
> +static int gen8_write_pdp_ctx(struct i915_hw_context *ctx,
> + struct i915_hw_ppgtt *ppgtt)
> +{
> + struct page *page;
> + uint32_t *reg_state;
> +
> + page = i915_gem_object_get_page(ctx->obj, 1);
> + reg_state = kmap_atomic(page);
> +
> + reg_state[CTX_PDP3_UDW+1] = ppgtt->pd_dma_addr[3] >> 32;
> + reg_state[CTX_PDP3_LDW+1] = ppgtt->pd_dma_addr[3];
> + reg_state[CTX_PDP2_UDW+1] = ppgtt->pd_dma_addr[2] >> 32;
> + reg_state[CTX_PDP2_LDW+1] = ppgtt->pd_dma_addr[2];
> + reg_state[CTX_PDP1_UDW+1] = ppgtt->pd_dma_addr[1] >> 32;
> + reg_state[CTX_PDP1_LDW+1] = ppgtt->pd_dma_addr[1];
> + reg_state[CTX_PDP0_UDW+1] = ppgtt->pd_dma_addr[0] >> 32;
> + reg_state[CTX_PDP0_LDW+1] = ppgtt->pd_dma_addr[0];
> +
> + kunmap_atomic(reg_state);
> +
> + return 0;
> +}
> +
> static int gen8_switch_context(struct intel_engine *ring,
> struct i915_hw_context *to0, u32 tail0,
> struct i915_hw_context *to1, u32 tail1)
> {
> + struct i915_hw_ppgtt *ppgtt;
> +
> BUG_ON(!i915_gem_obj_is_pinned(to0->obj));
>
> - if (to1)
> + ppgtt = ctx_to_ppgtt(to0);
> + gen8_write_pdp_ctx(to0, ppgtt);
> +
> + if (to1) {
> BUG_ON(!i915_gem_obj_is_pinned(to1->obj));
>
> + ppgtt = ctx_to_ppgtt(to1);
> + gen8_write_pdp_ctx(to1, ppgtt);
> + }
> +
You're always calling gen8_write_pdp_ctx() and gen8_write_tail_ctx()
together, kmapping the page twice is a bit wastful.
--
Damien
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