On Tue, 10 Jun 2025, Ankit Nautiyal <ankit.k.nauti...@intel.com> wrote:
> This reverts commit 584cf613c24a4250d9be4819efc841aa2624d5b6.
> Commit 584cf613c24a ("drm/i915/dp: Reject HBR3 when sink doesn't support
> TPS4") introduced a blanket rejection of HBR3 link rate when the sink does
> not support TPS4. While this was intended to address instability observed
> on certain eDP panels [1], the TPS4 requirement is only mandated for DPRX
> and not for eDPRX.
>
> This change inadvertently causes blank screens on some eDP panels that do
> not advertise TPS4 support, and require HBR3 to operate at their fixed
> native resolution.
>
> Revert the commit to restore functionality for such panels.
>
> [1] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5969
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
On the revert,
Acked-by: Jani Nikula <jani.nik...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 49 ++++---------------------
> 1 file changed, 7 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 208a953b04a2..2a0b76ae33cd 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -174,28 +174,10 @@ int intel_dp_link_symbol_clock(int rate)
>
> static int max_dprx_rate(struct intel_dp *intel_dp)
> {
> - struct intel_display *display = to_intel_display(intel_dp);
> - struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> - int max_rate;
> -
> if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
> - max_rate = drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);
> - else
> - max_rate =
> drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
> + return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);
>
> - /*
> - * Some broken eDP sinks illegally declare support for
> - * HBR3 without TPS4, and are unable to produce a stable
> - * output. Reject HBR3 when TPS4 is not available.
> - */
> - if (max_rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) {
> - drm_dbg_kms(display->drm,
> - "[ENCODER:%d:%s] Rejecting HBR3 due to missing TPS4
> support\n",
> - encoder->base.base.id, encoder->base.name);
> - max_rate = 540000;
> - }
> -
> - return max_rate;
> + return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
> }
>
> static int max_dprx_lane_count(struct intel_dp *intel_dp)
> @@ -4271,9 +4253,6 @@ static void intel_edp_mso_init(struct intel_dp
> *intel_dp)
> static void
> intel_edp_set_sink_rates(struct intel_dp *intel_dp)
> {
> - struct intel_display *display = to_intel_display(intel_dp);
> - struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> -
> intel_dp->num_sink_rates = 0;
>
> if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
> @@ -4284,7 +4263,10 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
> sink_rates, sizeof(sink_rates));
>
> for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
> - int rate;
> + int val = le16_to_cpu(sink_rates[i]);
> +
> + if (val == 0)
> + break;
>
> /* Value read multiplied by 200kHz gives the per-lane
> * link rate in kHz. The source rates are, however,
> @@ -4292,24 +4274,7 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
> * back to symbols is
> * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
> */
> - rate = le16_to_cpu(sink_rates[i]) * 200 / 10;
> -
> - if (rate == 0)
> - break;
> -
> - /*
> - * Some broken eDP sinks illegally declare support for
> - * HBR3 without TPS4, and are unable to produce a stable
> - * output. Reject HBR3 when TPS4 is not available.
> - */
> - if (rate >= 810000 &&
> !drm_dp_tps4_supported(intel_dp->dpcd)) {
> - drm_dbg_kms(display->drm,
> - "[ENCODER:%d:%s] Rejecting HBR3 due
> to missing TPS4 support\n",
> - encoder->base.base.id,
> encoder->base.name);
> - break;
> - }
> -
> - intel_dp->sink_rates[i] = rate;
> + intel_dp->sink_rates[i] = (val * 200) / 10;
> }
> intel_dp->num_sink_rates = i;
> }
--
Jani Nikula, Intel
