> -----Original Message-----
> From: Intel-gfx <intel-gfx-boun...@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Monday, June 9, 2025 7:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org
> Subject: [PATCH v4 03/21] drm/i915/dsb: Introduce intel_dsb_exec_time_us()
>
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> Pull the magic 20 usec DSB execution deadline into
> intel_dsb_arm_exec_time_us(), and also add its counterapart for the non-arming
Nit: Typo in counterpart
Change Looks Good to me.
Reviewed-by: Uma Shankar <uma.shan...@intel.com>
> register write section. For the non-arming part we'll just throw in a random
> 80 usec
> for now so the total is 100usec. The total exec time will be needed by the
> upcoming flip queue code.
>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dsb.c | 26 ++++++++++++++++++++++--
> drivers/gpu/drm/i915/display/intel_dsb.h | 1 +
> 2 files changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 8cbb5695c651..c8011f5e4076 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -686,14 +686,36 @@ static u32 dsb_error_int_en(struct intel_display
> *display)
> return errors;
> }
>
> +/*
> + * FIXME calibrate these sensibly, ideally compute based on
> + * the number of regisetrs to be written. But that requires
> + * measuring the actual DSB execution speed on each platform
> + * (and the speed also depends on CDCLK and memory clock)...
> + */
> +static int intel_dsb_noarm_exec_time_us(void)
> +{
> + return 80;
> +}
> +
> +static int intel_dsb_arm_exec_time_us(void) {
> + return 20;
> +}
> +
> +int intel_dsb_exec_time_us(void)
> +{
> + return intel_dsb_noarm_exec_time_us() +
> + intel_dsb_arm_exec_time_us();
> +}
> +
> void intel_dsb_vblank_evade(struct intel_atomic_state *state,
> struct intel_dsb *dsb)
> {
> struct intel_crtc *crtc = dsb->crtc;
> const struct intel_crtc_state *crtc_state =
> intel_pre_commit_crtc_state(state, crtc);
> - /* FIXME calibrate sensibly */
> - int latency = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
> 20);
> + int latency = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
> + intel_dsb_arm_exec_time_us());
> int start, end;
>
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
> b/drivers/gpu/drm/i915/display/intel_dsb.h
> index ab6489749866..6bcfb03f3415 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
> @@ -35,6 +35,7 @@ struct intel_dsb *intel_dsb_prepare(struct
> intel_atomic_state *state, void intel_dsb_finish(struct intel_dsb *dsb);
> void
> intel_dsb_gosub_finish(struct intel_dsb *dsb); void intel_dsb_cleanup(struct
> intel_dsb *dsb);
> +int intel_dsb_exec_time_us(void);
> void intel_dsb_reg_write(struct intel_dsb *dsb,
> i915_reg_t reg, u32 val);
> void intel_dsb_reg_write_indexed(struct intel_dsb *dsb,
> --
> 2.49.0
