From: Ville Syrjälä <ville.syrj...@linux.intel.com>
Attempt to deal with the fact that pipe DMCs can sometimes
lose their state.
Ville Syrjälä (9):
drm/i915/dmc: Limit pipe DMC clock gating w/a to just ADL/DG2/MTL
drm/i915/dmc: Parametrize MTL_PIPEDMC_GATING_DIS
drm/i915/dmc: Shuffle code around
drm/i915/dmc: Extract dmc_load_program()
drm/i915/dmc: Reload pipe DMC state on TGL when enabling pipe A
drm/i915/dmc: Reload pipe DMC MMIO registers for pipe C/D on PTL+
drm/i915/dmc: Assert DMC is loaded harder
drm/i915/dmc: Pass crtc_state to intel_dmc_{enable,disable}_pipe()
drm/i915/dmc: Do not enable the pipe DMC on TGL when PSR is possible
drivers/gpu/drm/i915/display/intel_display.c | 16 +-
.../i915/display/intel_display_power_well.c | 4 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 336 +++++++++++-------
drivers/gpu/drm/i915/display/intel_dmc.h | 7 +-
.../drm/i915/display/intel_modeset_setup.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 3 +-
6 files changed, 234 insertions(+), 134 deletions(-)
--
2.49.0
