[PATCH 6/9] drm/i915/dmc: Reload pipe DMC MMIO registers for pipe C/D on PTL+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrj...@linux.intel.com>

On PTL+ the pipe DMC on pipes C/D loses its MMIO state occasionally.
Not quite sure what the specific sequence is that makes this happen
(eg. simply disabling PG2 doesn't seem to be enough to trigger this
on its own).

Reload the MMIO registers for the affected pipes when enabling the
pipe DMC. So far I've not see this happen on PTL pipe A/B, nor on any
pipe on any other post-TGL platform.

The DMC program RAM doesn't appear to need manual restoring, though
Windows appears to be doing exactly that on most platforms (for some
of the pipes). None of this is properly documented anywhere it seems.

Reviewed-by: Uma Shankar <uma.shan...@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 32 +++++++++++++++++++-----
 1 file changed, 26 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c 
b/drivers/gpu/drm/i915/display/intel_dmc.c
index fd99c4645260..76b88c9bea02 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -575,8 +575,18 @@ static u32 dmc_mmiodata(struct intel_display *display,
                return dmc->dmc_info[dmc_id].mmiodata[i];
 }
 
-static void dmc_load_program(struct intel_display *display,
-                            enum intel_dmc_id dmc_id)
+static void dmc_load_mmio(struct intel_display *display, enum intel_dmc_id 
dmc_id)
+{
+       struct intel_dmc *dmc = display_to_dmc(display);
+       int i;
+
+       for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {
+               intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i],
+                              dmc_mmiodata(display, dmc, dmc_id, i));
+       }
+}
+
+static void dmc_load_program(struct intel_display *display, enum intel_dmc_id 
dmc_id)
 {
        struct intel_dmc *dmc = display_to_dmc(display);
        int i;
@@ -593,10 +603,7 @@ static void dmc_load_program(struct intel_display *display,
 
        preempt_enable();
 
-       for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {
-               intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i],
-                              dmc_mmiodata(display, dmc, dmc_id, i));
-       }
+       dmc_load_mmio(display, dmc_id);
 }
 
 static bool need_pipedmc_load_program(struct intel_display *display)
@@ -605,6 +612,17 @@ static bool need_pipedmc_load_program(struct intel_display 
*display)
        return DISPLAY_VER(display) == 12;
 }
 
+static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe 
pipe)
+{
+       /*
+        * On PTL pipe C/D PIPEDMC MMIO state is lost sometimes
+        *
+        * TODO figure out when exactly this happens, so far it
+        * didn't seem 100% deterministic...
+        */
+       return DISPLAY_VER(display) >= 30 && pipe >= PIPE_C;
+}
+
 void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe)
 {
        enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
@@ -614,6 +632,8 @@ void intel_dmc_enable_pipe(struct intel_display *display, 
enum pipe pipe)
 
        if (need_pipedmc_load_program(display))
                dmc_load_program(display, dmc_id);
+       else if (need_pipedmc_load_mmio(display, pipe))
+               dmc_load_mmio(display, dmc_id);
 
        if (DISPLAY_VER(display) >= 20) {
                intel_de_write(display, PIPEDMC_INTERRUPT(pipe), 
pipedmc_interrupt_mask(display));
-- 
2.49.0