From: Ville Syrjälä <ville.syrj...@linux.intel.com>
Initial stab at implementing the PIPEDMC based flip queue.
Briefly smoke tested on LNL and PTL-A0, not much more.
Still has quite a few warts..
v2: cleaned up a few of the warts at least
should work on PTL now
v3: Rebase due to DSB GOSUB stuff getting merged
Try to fix PKG_C_LATENCY
Ignore INT_VECTOR when opther PIPEDMC interrupt are present
v4: Fix up some DSB issues
Limit DMC clock gating w/as
Reload pipe C/D PIPEDMC MMIOs on PTL
Disable PSR in order to get a bit more CI coverage
v5: DMC and DSB fixes already merged
Drop the DMC halt w/a for PTL-B0+
Add some docs
Ville Syrjälä (9):
drm/i915: Set PKG_C_LATENCY.added_wake_time to 0
drm/i915: Try to program PKG_C_LATENCY more correctly
drm/i915/dmc: Define flip queue related PIPEDMC registers
drm/i915/flipq: Provide the nuts and bolts code for flip queue
drm/i915/flipq: Implement flip queue based commit path
drm/i915/flipq: Implement Wa_18034343758
drm/i915/flipq: Implement Wa_16018781658 for LNL-A0
drm/i915/flipq: Add intel_flipq_dump()
drm/i915/flipq: Enable flipq by default for testing
Documentation/gpu/i915.rst | 6 +
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 53 +-
.../gpu/drm/i915/display/intel_display_core.h | 6 +
.../drm/i915/display/intel_display_driver.c | 3 +
.../drm/i915/display/intel_display_params.c | 3 +
.../drm/i915/display/intel_display_params.h | 1 +
.../drm/i915/display/intel_display_types.h | 20 +
drivers/gpu/drm/i915/display/intel_dmc.c | 94 +++-
drivers/gpu/drm/i915/display/intel_dmc.h | 11 +
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 190 +++++++
drivers/gpu/drm/i915/display/intel_flipq.c | 484 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_flipq.h | 37 ++
drivers/gpu/drm/i915/display/skl_watermark.c | 109 ++--
drivers/gpu/drm/xe/Makefile | 1 +
15 files changed, 955 insertions(+), 64 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_flipq.c
create mode 100644 drivers/gpu/drm/i915/display/intel_flipq.h
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2.49.0
